Horizontally Aligned Semiconductor Channels via Vertical Stacking Transfer
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Solution Overview
Problem
Conventional methods for manufacturing semiconductor devices using Group III-V compound and germanium channels face inefficiencies in aligning and stacking n-type and p-type metal oxide semiconductors, as well as limitations in scaling due to the need for separate processes and material differences, which affect the precision and efficiency of channel layer transfer onto silicon substrates.
Innovation Solution
A method involving epitaxial stacking of Group III-V compound and germanium channels with different semiconductor characteristics vertically on a single substrate, followed by etching to separate them horizontally, allowing for a single transfer process onto a silicon substrate, utilizing sacrificial layers and barrier layers to manage lattice constants and strain for improved mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate processes are used to transfer n-MOS and p-MOS channel layers onto silicon substrate, then each channel type can be formed with optimized material properties, but the alignment precision and process efficiency deteriorate due to multiple transfer operations
Solution Approach 1:
The patent merges the transfer processes of n-MOS and p-MOS channel layers into a single simultaneous transfer operation. Multiple channel layers with different semiconductor characteristics are stacked vertically on a common sacrificial layer, allowing all layers to be transferred together in one step, thereby eliminating alignment errors associated with multiple separate transfer operations while maintaining material optimization for each channel type.
Solution Approach 2:
The patent transitions from horizontal separate transfer operations to vertical stacking architecture. By stacking channel layers vertically on top of each other before transfer, the system exploits the vertical dimension to enable simultaneous transfer of multiple channel types, converting a multi-step horizontal process into a single vertical stack transfer operation that maintains both material optimization and alignment precision.
2Ease of manufacture
If ion implantation is used to form n-MOS and p-MOS on silicon substrate, then the process is simple and well-established, but Group III-V compound semiconductor and germanium single crystals are fatally damaged
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary between the Group III-V/Ge channel layers and the silicon substrate. This sacrificial layer enables the formation of n-MOS and p-MOS without direct ion implantation into the sensitive Group III-V and Ge crystals. The ion implantation is performed into the sacrificial layer instead, which can be subsequently removed, thereby protecting the crystal integrity of the active semiconductor materials while still enabling doping through the intermediary medium.
Solution Approach 2:
The patent segments the doping function into two separate components: the sacrificial layer that receives the ion implantation damage, and the Group III-V/Ge channel layers that remain undamaged. This segmentation allows the harmful ion implantation process to be isolated to a disposable sacrificial layer, while the valuable semiconductor materials are protected and can be transferred intact to the final silicon substrate.
3Ease of manufacture
If conventional separate transfer processes are used for n-MOS and p-MOS, then each process can be independently optimized, but the overall productivity and process efficiency deteriorate due to repeated transfer operations
Solution Approach 1:
The patent combines multiple independent transfer processes into a single integrated transfer operation. By stacking n-MOS and p-MOS channel layers vertically on a common sacrificial layer structure, the system enables simultaneous transfer of all channel layers in one operation, thereby maintaining the flexibility to independently optimize each channel type's material properties while dramatically improving productivity by eliminating repeated transfer cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient alignment and stacking of channels with different semiconductor characteristics, improving electron and hole mobility by applying strain and reducing the need for precise alignment of n-MOS and p-MOS through separate processes, while allowing for various combinations of Group III-V compound channels and substrates during epitaxial growth.
Implementation Method 1
the channel layer 102 is bound to a silicon substrate 110 through wafer bonding
Implementation Method 2
the sacrificial layer 101 is etched to remove the sacrificial layer 101 in an epitaxial lift-off (ELO) mode
Implementation Method 3
a sacrificial layer 101 and channel layer 102 including a Group III-V compound are grown sequentially in an epitaxial mode on a substrate 100
Data Source
AI summary
Disclosed is a semiconductor device, which includes: forming a first channel layer including a Group III-V compound or germanium (Ge) and having a first semiconductor characteristics on a first substrate; forming a second channel layer including a Group III-V compound or germanium (Ge) and having a second semiconductor characteristics different from the first semiconductor characteristics on the first channel layer; forming a bonding layer containing an oxide on a second channel layer; allowing the bonding layer to be bound to the second substrate so that a structure including the bonding layer, the second channel layer, the first channel layer and the first substrate may be stacked on the second substrate; removing the first substrate stacked on the second substrate; and removing the first channel layer from a partial region of the structure stacked on the second substrate.