Horizontal Optical-Electric Chip Package for Signal Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional approaches for forming packages with optical and electric chips suffer from high complexity and signal distortion due to the need for compact and reliable integration of components with increasingly smaller spacings and harsh operational conditions.
Innovation Solution
A package design featuring a component carrier with both electrically conductive and insulating layers, where an optical chip and an electric chip are functionally coupled and embedded side-by-side within a horizontal plane, eliminating the need for vertical signal paths and promoting signal integrity through short signal paths and efficient heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If optical chip and electric chip are integrated vertically with stacked arrangement, then space utilization is improved, but signal path length increases and signal integrity deteriorates
Solution Approach 1:
The patent transitions from vertical stacking to horizontal side-by-side arrangement of optical and electric chips, changing the spatial dimension of integration. This dimensional shift maintains compact package volume while achieving shorter signal paths through the component carrier, thereby improving signal integrity without sacrificing space efficiency.
2Productivity
If contact spacing is reduced to increase component density, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent separates optical chip and electric chip into distinct side-by-side locations on the component carrier, with dedicated contact regions. This segmentation allows each chip type to have optimized contact spacing independently, enabling high component density while maintaining manageable manufacturing precision requirements for each separate contact group.
3Quantity of substance
If multiple layers of conductive and insulating structures are added to support higher component density, then component density is improved, but device complexity increases
Solution Approach 1:
The component carrier is designed with multi-functional regions that serve both mechanical support and electrical connection purposes. The side-by-side chip arrangement allows shared infrastructure elements (substrate, encapsulation, external interconnects) to support multiple contacts and chips, achieving high contact quantity while reducing overall device complexity through functional integration.
Data Source
Figure 1
Figure 2A~2B
Figure 3~4
AI summary
A package (100), wherein the package (100) comprises a component carrier (102) comprising at least one electrically conductive layer structure (104) and/or at least one electrically insulating layer structure (106), and an optical chip (108) and an electric chip (110) being functionally coupled with each other and being embedded side-by-side in the component carrier (102) so that a signal path (112) between the optical chip (108) and the electric chip (110) is within a horizontal plane.