Horizontal Connecting Structures for Stacked Substrates
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Solution Overview
Problem
Stacked CMOS chips face challenges with vertical dimension constraints in ultra-thin devices and limited flexibility in electrical connection alignment, leading to thickness issues and increased power dissipation.
Innovation Solution
A multi-layer horizontal connecting structure is fabricated inside a substrate of individual device tiers, using conductive layers with different patterns to reduce metal usage and thickness, allowing for flexible electrical connections between vertically stacked tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical interwafer via connections are used to connect multiple tiers, then electrical connections between device tiers are established, but chip thickness increases and power dissipation increases
Solution Approach 1:
The patent transitions from vertical via connections to horizontal connecting structures that route signals laterally within the substrate. This dimensional shift allows electrical connections to be made without increasing chip thickness, as the horizontal paths are contained within the substrate plane rather than extending vertically through multiple tiers.
Solution Approach 2:
The patent introduces an intermediary horizontal connecting structure that mediates between device tiers. Instead of direct vertical connections, signals are routed through horizontal conductive paths within the substrate that connect to contact points on different tiers, reducing the need for thick vertical vias and associated power dissipation.
2Reliability
If vertical interwafer via connections are used to connect multiple tiers, then electrical connections between device tiers are established, but power dissipation increases
Solution Approach 1:
By routing connections horizontally within the substrate rather than vertically through thick vias, the patent reduces the resistance and inductance of interconnect paths. This dimensional change lowers power dissipation while maintaining electrical connection reliability between device tiers.
Solution Approach 2:
The horizontal connecting structure acts as an intermediary that provides lower-resistance signal paths compared to vertical vias. This mediator reduces power dissipation by offering optimized routing paths that avoid the high resistance associated with thick vertical connections.
3Reliability
If conventional vertical connection methods are used, then electrical connections are established, but placement and routing flexibility is limited
Solution Approach 1:
The patent introduces horizontal routing paths within the substrate, adding a lateral dimension to connection routing. This enables flexible placement of contact points on device tiers while maintaining reliable electrical connections, as signals can be routed horizontally to accommodate various design layouts rather than being constrained to vertical alignment.
Solution Approach 2:
The horizontal connecting structure serves multiple functions: it provides electrical connections between tiers, enables flexible routing, and accommodates various device placements. This multi-functional approach enhances adaptability while maintaining connection reliability.
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first device tier including a first semiconductor substrate having a first plurality of devices. A second semiconductor substrate is formed over the first device tier. A first conductive layer is formed within the second semiconductor substrate, and a second conductive layer is formed within the second semiconductor substrate and over the first conductive layer. The first conductive layer and the second conductive layer have different patterns as viewed from a top-view. A second plurality of devices are formed on the second semiconductor substrate. The first and second conductive layers are configured to electrically couple the first plurality of devices and the second plurality of devices.