Horizontal Die Stack Interconnects for Low-Resistance 3D Packaging
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Solution Overview
Problem
Conventional semiconductor packages with vertically stacked dies experience increased die-to-die resistance as the number of dies in the stack increases, due to the inability to directly electrically connect non-adjacent dies, limiting the integration density and performance of three-dimensional integrated circuits.
Innovation Solution
The semiconductor package includes a die stack with vertically aligned and horizontally stacked dies that are directly electrically connected through a second die, utilizing a planar semiconductor substrate, dielectric structure, interconnect structure, and TSV structures to reduce die-to-die resistance, allowing for efficient intra- and inter-stack connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked dies are connected through intermediate dies, then three-dimensional integration is achieved, but die-to-die resistance increases as the number of dies increases
Solution Approach 1:
The patent transitions from vertical connection through intermediate dies to horizontal connection at the same die level. Dies are connected laterally within the same plane rather than stacking vertically through multiple intermediate layers, fundamentally changing the dimensional approach to inter-die connectivity.
Solution Approach 2:
The patent eliminates the need for intermediate dies as mediators by implementing direct lateral connections between adjacent dies at the same level. The interconnect structure provides direct electrical pathways without requiring intermediate connection layers or mediator dies.
2Quantity of substance
If more dies are stacked vertically, then integration density improves, but the length of interconnects between stacked chips increases
Solution Approach 1:
The patent shifts interconnect routing from the vertical dimension to the horizontal dimension. By connecting dies laterally at the same level rather than vertically through stacked layers, the interconnect length is significantly reduced while maintaining high integration density.
3Shape
If conventional vertical stacking is used, then three-dimensional package structure is achieved, but direct electrical connection between non-adjacent dies is not possible
Solution Approach 1:
The patent maintains the three-dimensional package structure while adding lateral connectivity at each die level. This creates a hybrid architecture where vertical stacking is combined with horizontal routing, enabling direct connections between any dies in the stack without increasing complexity.
Solution Approach 2:
The interconnect structure serves multiple functions simultaneously: it provides vertical connectivity through the stack, horizontal connectivity at each level, and direct pathways between non-adjacent dies. This multi-functional design simplifies the overall electrical connection architecture.
Data Source
AI summary
A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°.