Horizontal Gate All Around Device Structures
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Solution Overview
Problem
As transistor feature sizes shrink, there is a need to improve transistor device structures to enhance electrostatic coupling and reduce parasitic capacitance and off-state leakage, particularly in horizontal gate all around (hGAA) structures used in CMOS manufacturing.
Innovation Solution
The method involves forming a superlattice structure on a substrate with alternating layers, creating a lateral etch stop layer, and selectively etching to form voids, using a cluster tool with various processing chambers for precise control and deposition, ultimately forming a horizontal gate all around device structure with improved thickness control and defect-free stacked channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor feature sizes are shrunk to achieve greater circuit density, then circuit density increases, but electrostatic control deteriorates and parasitic capacitance increases
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanowire channels that wrap around the gate electrode. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sidewalls), providing superior electrostatic control while maintaining small footprint for high circuit density.
Solution Approach 2:
The patent implements a nested structure where the gate electrode is surrounded by the channel material, which is in turn surrounded by dielectric layers. The channel wraps around the gate in a nested configuration, enabling all-around gate control of the channel while maintaining compact vertical stacking for high density.
2Productivity
If transistor feature sizes are shrunk to achieve greater circuit density, then circuit density increases, but off-state leakage increases
Solution Approach 1:
The three-dimensional nanowire channel structure wrapping around the gate provides enhanced electrostatic control that suppresses off-state leakage. The all-around gate coverage enables better depletion of the channel in off-state, preventing leakage paths while maintaining the small feature sizes needed for high density.
3Reliability
If superlattice structure is selectively etched to form horizontal gate all around structure, then electrostatic control improves, but manufacturing complexity increases
Solution Approach 1:
The patent uses a superlattice structure consisting of alternating layers of different materials (e.g., Si/SiGe) that can be selectively etched. This segmentation into etchable and non-etchable layers enables selective removal of specific materials to form the horizontal gate all-around structure while leaving the channel-forming layers intact.
Solution Approach 2:
The patent exploits differences in material parameters (etch selectivity) between alternating layers of the superlattice. By choosing materials with contrasting etch rates, the process achieves selective removal of sacrificial layers to create the desired three-dimensional structure, simplifying the manufacturing of complex hGAA devices.
4Manufacturing precision
If lateral etch stop layer is formed by epitaxial deposition or selective oxidation, then thickness control improves, but process steps increase
Solution Approach 1:
The lateral etch stop layer is formed through self-aligned epitaxial deposition or selective oxidation processes. The etch stop layer material is deposited or grown in situ on specific surfaces, automatically positioning itself where needed without requiring separate alignment steps, thus achieving precise thickness control while minimizing additional process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a thin body device with enhanced thickness control, increased circuit density, and improved electrostatic control, addressing the challenges of parasitic capacitance and off-state leakage in hGAA structures.
Implementation Method 1
forming a superlattice structure atop a top surface of a substrate, wherein the superlattice structure comprises a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs
Implementation Method 2
forming a lateral etch stop layer by epitaxial deposition of a material of the first layer or the second layer of the superlattice structure atop a sidewall of the superlattice structure, or by selectively oxidizing edges of the first layers and second layers of the superlattice structure
Data Source
AI summary
A method of forming a semiconductor device includes: forming a superlattice structure atop the top surface of a substrate, wherein the superlattice structure comprises a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs; forming a lateral etch stop layer by epitaxial deposition of a material of the first layer or the second layer of the superlattice structure atop a sidewall of the superlattice structure, or by selectively oxidizing edges of the first layers and second layers of the superlattice structure; subsequently forming a source region adjacent a first end of the superlattice structure and a drain region adjacent a second opposing end of the superlattice structure; and selectively etching the superlattice structure to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure.