Horizontal Gate-All-Around Semiconductor Devices with Anti-Punch Through Layers
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Solution Overview
Problem
Current semiconductor device fabrication techniques face challenges in scaling integrated circuits due to limitations in preventing punch-through between source and drain regions, which affects device performance and reliability.
Innovation Solution
The formation of a semiconductor device with a horizontal gate all around structure, including a high dose anti-punch through (APT) layer and channel layers, where the APT layer is formed prior to channel layers, and a barrier layer is used to prevent punch-through and minimize back-diffusion, along with shallow trench isolation and metal gate formation to reduce parasitic capacitance and bridge risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication techniques are used for scaling, then manufacturing process remains simple, but punch-through between source and drain regions occurs affecting device performance
Solution Approach 1:
The channel region is segmented into multiple horizontal channels stacked vertically, with each channel surrounded by its own gate structure. This segmentation allows independent control of each channel and prevents punch-through by confining carriers within individual channels separated by insulating materials.
Solution Approach 2:
The gate structure is wrapped around each horizontal channel in a nested configuration, with the gate completely surrounding the channel cross-section. This nested gate-all-around structure provides superior electrostatic control and prevents punch-through by fully isolating the channel from source and drain regions.
2Productivity
If channel length is reduced for scaling, then device density increases, but punch-through between source and drain regions increases
Solution Approach 1:
The invention transitions from planar channel structures to three-dimensional horizontal channels stacked in the vertical dimension. This dimensional change allows continued scaling and increased device density while maintaining adequate channel length for each individual horizontal channel, thereby preventing punch-through through enhanced gate control in the third dimension.
Solution Approach 2:
Insulating materials and barrier layers are introduced as intermediary structures between source and drain regions, and between adjacent horizontal channels. These intermediaries prevent direct carrier transport paths that would cause punch-through, allowing shorter effective channel lengths while maintaining reliability.
3Reliability
If standard gate structures are used, then fabrication is simpler, but parasitic capacitance remains high affecting performance
Solution Approach 1:
The gate structure adopts a curved, wraparound configuration that completely surrounds each horizontal channel cross-section. This spherical-like gate-all-around structure maximizes the gate's electrostatic control over the channel, reducing parasitic capacitance by minimizing uncovered channel surfaces while maintaining compact fabrication through conformal deposition processes.
Data Source
AI summary
A semiconductor device having a horizontal gate all around structure is provided. The semiconductor device includes a substrate and a fin. The fin is disposed on the substrate, and includes an anti-punch through (APT) layer formed of a material at a dose of about 1E18 atoms/cm2 to about 1E19 atoms/cm2, and a barrier layer formed above the APT layer. A method of forming a semiconductor device having a horizontal gate all around structure is also provided.