Horizontal Gate-All-Around Transistors with Wrapped Source/Drain
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Solution Overview
Problem
The fabrication of horizontal gate-all-around (HGAA) transistors is challenging, particularly in forming satisfactory source and drain (S/D) regions at small device pitches, such as 40 nanometers or smaller, due to limitations in current methods.
Innovation Solution
A method for forming semiconductor devices, including HGAA devices, involves forming fins with alternately stacked semiconductor layers, creating a dummy gate stack, and epitaxially growing a semiconductor layer that wraps around the S/D regions to form S/D features, allowing for tighter integration and smaller pitch without merging adjacent features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional source and drain formation methods are used for HGAA transistors, then the fabrication process is simpler, but the device pitch cannot be reduced to 40 nanometers or smaller
Solution Approach 1:
The source and drain regions are formed as separate, non-contiguous structures wrapped around the channel by alternating semiconductor layers, rather than as continuous regions. This segmentation allows precise positioning at small pitch dimensions while maintaining electrical isolation and functionality.
Solution Approach 2:
The source and drain regions are nested within the gate-all-around structure, with the gate completely surrounding the channel region. The alternating semiconductor layers are nested concentrically, with each layer wrapped around the previous one, creating a compact structure that achieves small pitch without merging adjacent features.
2Manufacturing precision
If source and drain regions are formed with conventional methods, then the device structure is simpler, but integration density decreases
Solution Approach 1:
The source and drain structures transition from planar, two-dimensional regions to three-dimensional wrapped-around structures. The alternating semiconductor layers create a radial arrangement where S/D regions surround the channel from multiple directions, increasing integration density by utilizing vertical and radial dimensions rather than only horizontal spacing.
Solution Approach 2:
The device structure combines multiple semiconductor materials with different properties in an alternating layered arrangement. This composite structure allows the S/D regions to have tailored electrical characteristics while maintaining the wrapped-around geometry, achieving both high integration density and optimized device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of S/D features with a narrow profile, increasing integration density and allowing for smaller fin-to-fin spacing, thereby improving the scalability and flexibility of HGAA devices within existing CMOS fabrication flows.
Implementation Method 1
epitaxially growing a semiconductor layer that wraps around the S/D regions to form S/D features
Data Source
AI summary
Various transistors, such as horizontal gate-all-around transistors, and methods of fabricating such are disclosed herein. An exemplary transistor includes a first nanowire and a second nanowire that include a first semiconductor material, a gate that wraps a channel region of the first nanowire and the second nanowire, and source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire. The source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material. In some implementations, the transistor further includes a fin-like semiconductor layer disposed over a substrate. The first nanowire and the second nanowire are disposed over the fin-like semiconductor layer, such that the first nanowire, the second nanowire, and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction. The fin-like semiconductor layer includes a third semiconductor material that is configured differently than the first semiconductor material.