Horizontal Gate Volatile Memory Cell With Bulk Traps
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Solution Overview
Problem
Conventional DRAM memory cells are difficult and expensive to integrate into high-speed and high-density memory devices due to performance constraints on transistors and capacitors, particularly in volatile memory cells like Z-RAM which rely on the floating body effect for capacitance.
Innovation Solution
A horizontal gate volatile memory cell with an n-channel field effect transistor (MOSFET) using a gate insulating layer of oxygen-rich non-stoichiometric silicon oxy-nitride with high density bulk traps, allowing for efficient charge storage and reduced manufacturing costs in high volume production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM memory cells with select transistor and storage capacitor are used, then the memory cell structure is well-established, but the manufacturing cost and integration difficulty increase for high-density applications
Solution Approach 1:
The patent extracts and eliminates the separate storage capacitor component from the memory cell structure. Instead of using a dedicated capacitor, the invention utilizes the floating body effect in the transistor itself to store charge, thereby reducing the number of components and simplifying the manufacturing process while maintaining memory functionality
Solution Approach 2:
The transistor structure is designed to perform multiple functions: it serves as both the access transistor and the storage element through the floating body effect. This multi-functionality eliminates the need for separate capacitor components and reduces overall device complexity, making it easier to integrate into high-density memory arrays
2Device complexity
If Z-RAM memory cells relying on floating body effect are used, then the capacitor component is eliminated, but the manufacturing precision and reliability constraints increase
Solution Approach 1:
The patent modifies the transistor parameters by introducing a lightly-doped drain (LDD) structure and optimizing the body doping concentration to create the floating body effect. These parameter changes enable charge storage functionality without requiring separate capacitors, while the LDD structure helps control short-channel effects and improves manufacturing yield
Solution Approach 2:
The lightly-doped drain (LDD) structure serves as an intermediary element that mediates between the source and heavily-doped drain regions. This intermediate doping layer helps control the electric field distribution, reduces hot carrier effects, and enables reliable floating body effect operation while maintaining manufacturing feasibility
3Quantity of substance
If high-density memory integration is pursued, then the storage capacity increases, but the manufacturing cost and difficulty increase
Solution Approach 1:
The patent merges the access transistor and storage capacitor functions into a single transistor structure utilizing the floating body effect. This consolidation reduces the area per memory cell and eliminates the need for separate capacitor fabrication processes, thereby enabling higher density integration while reducing manufacturing complexity and cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the creation of high-density, low-cost DRAM memory cells with improved charge storage capacity and operational efficiency, facilitating faster and more reliable memory device production.
Implementation Method 1
a gate insulating layer (103) sharing an interface (105) with the substrate (101) so that the source region (102) and the drain region (112) are situated at either end of the interface, wherein the gate insulating layer (103) comprises oxygen-rich non-stoichiometric silicon oxy-nitride with a high density of bulk traps
Implementation Method 2
the gate insulating layer (103) comprises oxygen-rich non-stoichiometric silicon oxy-nitride with a high density of bulk traps
Data Source
Figure 1~2
Figure 3a~3b
Figure 4
AI summary
A memory cell (100) comprising a transistor, the transistor comprising a substrate (101), a first source/drain region (102), a second source/drain region (112), a gate (104) and a gate insulating layer (103) positioned between the substrate (101) and the gate (104), wherein the gate insulating layer (103) is in a direct contact with the substrate (101) and comprises charge traps (131) distributed over an entire volume of the gate insulating layer (101).