Horizontal MEMS-IC Integration Using Monocrystalline Silicon
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Solution Overview
Problem
Current methods for co-integrating MEMS/NEMS with integrated circuits, such as the 'intermediate-CMOS' approach, restrict the choice of materials for MEMS structures and pose challenges in thermal management and stress optimization, limiting the performance and integration density of the devices.
Innovation Solution
A method where MEMS structures are integrated substantially 'horizontally' within the integrated circuit, using materials and layers from the CMOS process, such as semiconductor-based layers, for encapsulation, allowing for the use of monocrystalline silicon and enabling advanced microelectronic technologies without damaging the MEMS during production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the 'intermediate-CMOS' approach is used for co-integration, then the N/MEMS can be produced close to the CMOS circuit, but the choice of materials for N/MEMS structures is restricted and thermal budget constraints limit the production options
Solution Approach 1:
The substrate is divided into a first portion for N/MEMS production and a second portion for CMOS circuit production, allowing independent material selection and process optimization for each component type while maintaining physical integration on the same substrate
Solution Approach 2:
The patent transitions from vertical integration (stacking N/MEMS above CMOS) to horizontal integration (placing N/MEMS and CMOS side-by-side on the same substrate plane), enabling independent material selection while maintaining close integration for signal routing
2Ease of manufacture
If N/MEMS structures are produced using metallic interconnection layers, then integration with CMOS is achieved, but residual stresses and high coefficients of thermal expansion degrade N/MEMS reliability
Solution Approach 1:
The patent changes the material parameter from metallic interconnection layers to semiconductor-based layers (such as silicon) for N/MEMS structures, fundamentally altering the thermal and mechanical properties to reduce thermal expansion coefficients and residual stresses while maintaining CMOS compatibility through standard semiconductor fabrication processes
3Reliability
If additional encapsulation steps are added to protect N/MEMS, then reliability against contaminants is improved, but manufacturing costs and process complexity increase
Solution Approach 1:
The patent merges the N/MEMS encapsulation function with the CMOS circuit production process by using the same semiconductor-based layers and fabrication steps for both components, eliminating the need for separate encapsulation processes while maintaining protection and reducing overall device complexity
Solution Approach 2:
The semiconductor-based layers serve multiple functions simultaneously: they form the structural basis for N/MEMS devices, provide encapsulation protection, and enable CMOS circuit fabrication, replacing the need for separate dedicated encapsulation layers and processes
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
The invention relates to a method for production of a device (100), comprising at least one integrated circuit (104) and at least one N/MEMS (122), comprising at least the following steps: production of the N/MEMS in at least one upper layer (116) arranged at least above a first section of a substrate (120), production of the integrated circuit in a second section of the substrate and/or in a semiconductor layer arranged at least above the second section of the substrate and further comprising the production of a cover (124) encapsulating the N/MEMS from at least one layer used for the production of a grid (114) in the integrated circuit and/or for the production of at least one electrical contact(128, 130, 132, 134) of the integrated circuit.