Memory Circuitry With Horizontal Transistors for Stable Via Formation
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently forming vertically-stacked memory cells with conductive vias that maintain structural integrity and electrical connectivity, particularly in three-dimensional memory arrays.
Innovation Solution
The formation of vertically-alternating insulative tiers and memory-cell tiers with horizontal transistors, where conductive vias are created by replacing channel material with conductive material in specific contact openings, ensuring electrical coupling between access lines and reducing the risk of tier collapse during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form conductive vias in vertically-stacked memory cells, then structural integrity may be compromised due to tier collapse during etching, but the patent does not specify a particular conventional measure that improves another parameter
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before etching the contact opening. The mandrel is deposited and patterned to define the future via location, providing structural support during subsequent etching operations. This preliminary structure prevents tier collapse while enabling precise via formation, resolving the contradiction between reliability and ease of manufacture
Solution Approach 2:
The mandrel acts as an intermediary element during the via formation process. It serves as both a structural support to prevent collapse and a template for defining the via geometry. The mandrel is temporarily present during critical operations and is removed after serving its protective and guiding functions, enabling reliable via formation without compromising structural integrity
2Reliability
If contact openings are etched through multiple alternating tiers to form conductive vias, then electrical connectivity can be achieved, but the risk of tier collapse increases during the etching process
Solution Approach 1:
The mandrel is formed in advance of the contact opening etch, providing a structural framework that supports the alternating tiers during the etching process. This preliminary structure allows the etch to proceed through multiple tiers to achieve electrical connectivity while preventing collapse, thus resolving the contradiction between connectivity and structural stability
Solution Approach 2:
The mandrel structure provides beforehand cushioning by being in place before the etching operation begins. It acts as a protective element that cushions against the mechanical stresses of etching through multiple tiers, preventing structural failure while enabling the creation of electrically conductive pathways
Data Source
AI summary
A method used in forming memory circuitry comprising memory cells comprises forming vertically-alternating insulative tiers and memory-cell tiers. The memory cells individually comprise a horizontal transistor comprising a gate and channel material operatively-proximate the gate. The gate comprises part of one of a plurality of horizontal conductive access lines that individually directly electrically couple together multiple of the gates of different ones of the horizontal transistors that are in the same memory-cell tier. The access lines and channel material extend horizontally from the memory-array region into a connection region. Through a contact opening in the connection region, the channel material in the connection region is replaced with conductive material. The conductive material is directly against one of the access lines in the connection region and comprises part of a conductive-via construction in the connection region. Structure independent of method is also disclosed.