Horizontal Trench Power MOS Transistor Integration

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Solution Overview

Problem

Conventional power MOS transistors with vertical structures, such as VDMOS and UMOS, are large and costly to manufacture, making them unsuitable for integration with logic circuits on a CMOS-processed chip, as they fail to combine high breakdown voltage, high current output, and high operation speed with a horizontal structure.

Innovation Solution

A trench-typed power MOS transistor with a horizontal structure, comprising a drain region, double diffusion doping region, trench-typed gate region, source region, well region, deep well region, and substrate region, where the insulating layer forms thin and thick sidewall regions to reduce resistance and enhance breakdown voltage, allowing for integration with logic circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If vertical structure (VDMOS or UMOS) is adopted to achieve high breakdown voltage and high current output, then power MOS transistor can provide high power, but the device size becomes large and manufacturing cost increases

Engineering Contradiction:
Improvepower outputVSAvoiddevice area
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The patent transitions from vertical current flow (VDMOS/UMOS) to horizontal current flow by etching trenches laterally into the substrate. The gate electrode is positioned horizontally above the channel region, and current flows horizontally from source to drain regions, enabling high power output with reduced device area and compatibility with planar CMOS processing

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The device is segmented into distinct functional regions: trench region with gate electrode for field control, source region for carrier injection, drain region for current collection, and isolation regions. This segmentation allows optimized performance in each region while maintaining compact overall device footprint

Inventive Principle:
Principle #1Segmentation

2Reliability

If vertical structure (VDMOS or UMOS) is adopted to achieve high breakdown voltage, then power MOS transistor can operate under high voltage, but it cannot be integrated with logic circuits on CMOS-processed chip

Engineering Contradiction:
Improvebreakdown voltageVSAvoidintegrability with logic circuits
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The horizontal trench MOSFET structure serves multiple functions: the trench configuration provides high breakdown voltage through vertical field control, the planar topology enables CMOS compatibility and integration with logic circuits, and the gate electrode structure delivers high current output capability. This universal structure combines features of both vertical and planar devices

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Power

If multiple power MOS transistor cells are combined to output large current, then current output increases, but the device size becomes very large

Engineering Contradiction:
Improvecurrent outputVSAvoiddevice area
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

Multiple transistor functions are merged into a single horizontal trench structure. The gate electrode controls a channel that carries high current horizontally, eliminating the need for parallel vertical structures. The shared trench and gate configuration achieves high current output with significantly reduced area compared to combining multiple vertical cells

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8211766B2Method of fabricating a trench power MOS transistor
Publication Date: 2012.07.03 PTEK TECH
  • US8211766B2 patent drawing
  • US8211766B2 patent drawing
  • US8211766B2 patent drawing

AI summary

A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region.