Horizontal Word Line Semiconductor Structure for Low-Resistance DRAM
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Solution Overview
Problem
As the dimension of semiconductor memory structures like DRAM is reduced, the internal resistance increases due to vertical word line structures, affecting electrical performance and complicating the manufacturing process.
Innovation Solution
A semiconductor structure with a horizontal word line structure, where word lines extend parallel to the substrate surface, reducing internal resistance and simplifying the manufacturing process by eliminating the need for additional etching steps, and improving electrical performance through reduced capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a vertical word line structure is used in reduced-dimension memory, then the memory can maintain three-dimensional architecture for high density, but the internal resistance becomes excessively high, degrading electrical performance
Solution Approach 1:
The patent transitions from vertical word lines (z-direction) to horizontal word lines (x-direction parallel to substrate), fundamentally changing the dimensional orientation. This allows word lines to extend laterally across multiple channel areas at each stack level, reducing resistance while maintaining 3D vertical stacking for density.
2Reliability
If horizontal word line structure is implemented, then internal resistance and capacitive coupling are reduced, but additional process steps may be required
Solution Approach 1:
The patent combines the word line formation with the existing trench isolation etching step. The same etching process that creates isolation trenches also creates openings for horizontal word lines, merging two process steps into one and eliminating additional etching complexity.
3Reliability
If continuous word lines covering multiple channel areas are formed, then electrical connectivity is improved, but capacitive coupling between adjacent word lines increases
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary between adjacent horizontal word lines. This dielectric medium reduces capacitive coupling while allowing the word lines to maintain continuous coverage over multiple channel areas for improved electrical connectivity.
Data Source
AI summary
A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a laminate structure arranged on the substrate and including first semiconductor layers spaced apart from each other in a direction perpendicular to a top surface of the substrate, each first semiconductor layer including channel areas spaced apart from each other in a first direction, and first doped areas and second doped areas, each first doped area being arranged on one side of a respective one of the channel areas in a second direction, each second doped area being arranged on another side of the respective one of the channel areas in the second direction; and a word line structure including word lines extending in the first direction, an edge of each word line being flush with en edge of a respective one of the channel areas in the second direction.