Host Attach Logic for Translation Invalidation in Accelerator Caches
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Solution Overview
Problem
The integration of accelerator units with traditional CPU-based data processing systems faces bandwidth bottlenecks and high-latency issues due to suboptimal communication strategies, particularly in handling the computational demands of emerging workloads like cognitive computing, where traditional I/O attach methods like PCIe are inadequate.
Innovation Solution
An integrated circuit with host attach logic that couples an accelerator unit to a coherent data processing system, utilizing a real address-based directory and effective address-based accelerator cache, allowing for efficient translation entry invalidation and memory management by issuing requests through a host tag, thereby optimizing communication between the accelerator and system memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional PCIe I/O attach strategy is used to integrate accelerator units, then compatibility with existing systems is maintained, but bandwidth bottlenecks and high latency occur
Solution Approach 1:
The patent introduces host attach logic as an intermediary component between the accelerator unit and the coherent data processing system. This intermediary implements a translation cache that caches address translation entries and an invalidation cache that tracks invalidation requests, thereby mediating communication between the accelerator and system memory while avoiding the bandwidth and latency limitations of traditional PCIe interfaces.
2Reliability
If translation entry invalidation is performed without caching, then memory coherence is maintained, but communication latency increases
Solution Approach 1:
The patent implements an invalidation cache that pre-tracks and caches information about invalidation requests before they need to be processed. By maintaining this invalidation information in advance in the cache, the system can quickly process invalidation operations when they occur, reducing the time delay while ensuring memory coherence is properly maintained.
Solution Approach 2:
The invalidation cache acts as an intermediary structure between the translation cache and system memory. It caches invalidation request information and coordinates the invalidation process, allowing the system to maintain memory coherence while significantly reducing the latency associated with invalidation operations compared to direct memory access.
3Measurement precision
If a real address-based directory is used instead of effective address, then address translation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent introduces host attach logic with a translation cache as an intermediary layer between the accelerator unit's effective address space and the system memory's real address space. This translation cache stores address translation entries that map effective addresses to real addresses, providing accurate address translation while keeping the accelerator unit itself relatively simple and agnostic of the underlying address space.
Data Source
AI summary
An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit includes request logic that, responsive to receipt on the first communication interface of a translation entry invalidation request, issues to the accelerator unit via the second communication interface an invalidation request that identifies an entry in the effective address-based accelerator cache to be invalidated utilizing a host tag identifying a storage location in the real address-based directory.