Disaggregated Memory Prefetching With Host-Aware Access Filtering
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Solution Overview
Problem
In disaggregated memory environments, existing prefetching algorithms are ineffective due to a lack of knowledge about the allocation patterns across multiple memory sub-systems, leading to increased latency and reduced data integrity, as each sub-system operates independently without awareness of other sub-systems.
Innovation Solution
Implement memory sub-system aware prefetching using physical address tables that identify host and application identities, allowing the prefetch prediction engine to filter out irrelevant access operations and predict future memory access locations more accurately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing prefetching algorithms are used in disaggregated memory environments, then each memory sub-system can operate independently, but prefetching accuracy deteriorates due to lack of knowledge about allocation patterns across multiple sub-systems
Solution Approach 1:
The patent merges information from multiple memory sub-systems into a unified virtual address space. The virtual address manager consolidates allocation patterns and mapping information across disaggregated memory sub-systems, enabling the prefetching engine to access comprehensive allocation knowledge that spans multiple sub-systems, thereby improving prefetching accuracy without requiring each sub-system to operate in isolation
2Speed
If memory sub-systems operate independently without awareness of other sub-systems, then system complexity is reduced, but memory access latency increases due to ineffective prefetching
Solution Approach 1:
The patent introduces a virtual address manager as an intermediary component that mediates between memory sub-systems and the prefetching engine. This intermediary consolidates allocation pattern information and virtual-to-physical address mappings, enabling effective prefetching across disaggregated memory sub-systems without requiring direct complex inter-subsystem communication, thus reducing memory access latency while managing complexity through a centralized coordination point
3Reliability
If prefetching is performed without filtering irrelevant access operations, then processing overhead is reduced, but prefetching accuracy deteriorates due to noise in the input data
Solution Approach 1:
The patent extracts and filters relevant memory access operations from the overall stream of operations by utilizing the virtual address manager's knowledge of allocation patterns. The prefetching engine selectively processes only those access operations that are relevant to the current allocation context, filtering out irrelevant or noisy operations. This extraction of relevant information improves prefetching accuracy while managing complexity through pattern-based selection criteria
Data Source
AI summary
A processing device in a memory sub-system receives a first set of requests to access first data stored at a first set of physical addresses. The processing device identifies, using a physical address table comprising information about (i) a host and (ii) an application assigned to respective sets of physical addresses, a first host identity and a first application identity corresponding to the first set of physical addresses. The processing device further provides the first set of requests, the first host identity and the first application identity to a prefetch prediction engine. The processing device receives an output of the prefetch prediction engine, the output comprising a first memory address for prefetching second data from the first set of physical addresses to fulfill a second set of requests.