Host Bit-String Conversion for Precision and Memory Trade-Offs

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Solution Overview

Problem

Current memory systems face limitations in performing arithmetic operations due to the finite memory resources and the need for different precision levels, particularly when using the IEEE 754 floating-point format, which can lead to inefficiencies in processing and storage requirements.

Innovation Solution

A host-based conversion component is deployed to convert bit strings between formats, such as floating-point and posit formats, allowing for improved precision and reduced storage needs by utilizing hardware circuitry to perform operations directly on the host computing system, facilitating faster and more accurate calculations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If IEEE 754 floating-point format is used for arithmetic operations, then compatibility and ease of operation are improved, but precision is limited and storage requirements increase

Engineering Contradiction:
Improveease of operationVSAvoidprecision
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent changes the format parameter from IEEE 754 floating-point to alternative representations (such as fixed-point or custom formats) to achieve different precision characteristics. This allows the system to optimize for either higher precision or more efficient processing depending on the application requirements, directly addressing the trade-off between ease of operation and precision.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If higher precision arithmetic operations are performed, then measurement precision is improved, but processing time and device complexity increase

Engineering Contradiction:
ImproveprecisionVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the arithmetic operation process into multiple stages, performing different types of operations in parallel or sequentially based on precision requirements. This allows high-precision operations to be performed only when necessary, while lower-precision operations handle routine calculations, thereby reducing overall processing time while maintaining required precision levels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs partial precision operations by using different precision levels for different parts of the computation. Instead of uniformly applying high precision to all operations, the patent applies higher precision only to critical calculations where it is most needed, reducing the total computational burden and processing time.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If memory resources are increased to support higher precision operations, then precision is improved, but quantity of substance (memory capacity) increases

Engineering Contradiction:
ImproveprecisionVSAvoidmemory capacity
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent implements dynamic precision adjustment where the system can switch between different precision modes based on the current computational requirements and available memory resources. This allows the same memory infrastructure to support both high-precision and low-precision operations, optimizing memory utilization without requiring dedicated high-capacity storage for maximum precision operations.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11080017B2Host-based bit string conversion
Publication Date: 2021.08.03 MICRON TECHNOLOGY INC
  • US11080017B2 patent drawing
  • US11080017B2 patent drawing
  • US11080017B2 patent drawing

AI summary

Systems, apparatuses, and methods related to host-based bit string conversion are described. A conversion component may be deployed on a host computing system and configured to perform operations on bit strings to selectively convert the bit string between various numeric formats, such as floating-point and/or universal number (e.g., posit) formats. The conversion component may comprise a processing device that may be coupled to one or more memory resources. The memory resource of the conversion component may be configured to receive a bit string having a first format. The processing device of the conversion component coupled to the memory resource may be configured to format or convert the bit string to a second format.