Host Memory Buffer Updates Using One-Way PCIe Traffic

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Solution Overview

Problem

Updating data in a host memory buffer involves two-way traffic on a bus, which creates additional overhead and impacts performance, especially for short updates.

Innovation Solution

Utilizing one-way bus traffic to write updates to a dedicated space in the host memory buffer and employing a host-assisted copy operation to transfer the updates to the original location after error checking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two-way bus traffic is used to update data in host memory buffer, then data can be read and written back, but bus overhead increases and performance deteriorates

Engineering Contradiction:
Improvedata update correctnessVSAvoidupdate performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the host memory buffer into two distinct regions: a first region for original data storage and a second region for update operations. This allows update operations to occur in the second region without interfering with reads from the first region, enabling parallel operations and reducing bus traffic overhead while maintaining data integrity through subsequent copy-back operations.

Inventive Principle:
Principle #1Segmentation

2Reliability

If two-way bus traffic is used for data updates, then full read-modify-write cycle is completed, but bus latency increases

Engineering Contradiction:
Improvedata consistencyVSAvoidupdate latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary write operations to the second region of the host memory buffer before the actual update is needed in the first region. By pre-positioning update data in the second region and using background copy operations, the system reduces the critical path latency for update operations while ensuring data consistency through coordinated copy-back mechanisms.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If dedicated update space is used in host memory buffer, then one-way bus traffic can be implemented, but buffer management complexity increases

Engineering Contradiction:
Improvebus utilization efficiencyVSAvoidbuffer management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a second region in the host memory buffer as an intermediary space between the data storage device and the first region. This intermediary region facilitates one-way bus traffic for update operations, allowing data to be written once and then copied back when needed, thereby improving bus utilization efficiency while the complexity is managed through coordinated control between host and device.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12608307B2Data storage device and method for writing updates to a host memory buffer using assistance from a host
Publication Date: 2026.04.21 SANDISK TECHNOLOGIES LLC
  • US12608307B2 patent drawing
  • US12608307B2 patent drawing
  • US12608307B2 patent drawing

AI summary

A data storage device and method are disclosed for writing updates to a host memory buffer using assistance from a host. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The one or more processors, individually or in combination, are configured to: write data in a first location in the host memory buffer, wherein the first location is allocated for exclusive use by the data storage device; and write a plurality of updates to the data in a second location in the host memory buffer using one-way traffic on a bus between the data storage device and the host, wherein the second location is allocated for host memory buffer updates. The host is configured to copy the plurality of updates from the second location to the first location. Other embodiments are provided.