Host Bus Adaptor Full Duplex Data Transfer via FIS Sequencing
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Solution Overview
Problem
Current storage devices using nonvolatile memory, such as SSDs, face limitations in achieving full duplex data transfer capabilities due to the difference between external full duplex and internal half-duplex interfaces, which restricts data transfer speed and efficiency.
Innovation Solution
A data transfer method and system that employs a host bus adaptor to communicate externally via a full duplex interface and internally via a half-duplex interface, utilizing a frame information structure (FIS) sequence to enable simultaneous read and write operations, allowing for full duplex data transfer while generating FIS sequences according to the internal interface after data transfer is completed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a storage device uses a half-duplex internal interface to communicate between the host bus adaptor and nonvolatile memory, then the device complexity is reduced and compatibility is improved, but the data transfer speed is limited and cannot achieve full duplex capability
Solution Approach 1:
The patent segments the data transfer process into two independent channels: a first channel for write operations and a second channel for read operations. The host bus adaptor independently manages each channel, allowing simultaneous full-duplex data transfer between the host and nonvolatile memory, thereby resolving the contradiction between transfer speed and interface adaptability.
Solution Approach 2:
The patent introduces a temporal dimension to the data transfer by implementing pipelined operations where write and read commands are issued in different time slots through the half-duplex internal interface. This allows the system to achieve full-duplex functionality from a half-duplex interface by utilizing time-division multiplexing at the command level.
2Productivity
If the host bus adaptor issues write and read commands simultaneously through a half-duplex internal interface, then full duplex data transfer is achieved, but frame information structure sequence errors may occur
Solution Approach 1:
The patent implements a feedback mechanism where the host bus adaptor monitors the state of the internal interface and dynamically adjusts the timing of FIS generation. When a write command is issued, the adaptor waits for the write operation to complete before generating the corresponding FIS, ensuring proper sequencing and preventing errors while maintaining high transfer efficiency.
Solution Approach 2:
The host bus adaptor performs preliminary actions by pre-managing command queues and pre-scheduling FIS generation timing. Before actual data transfer occurs, the adaptor prepares the sequence of operations and ensures that FIS will be generated at the appropriate moments, preventing sequence errors while enabling efficient full-duplex operation.
Data Source
AI summary
A data transfer method of a storage device which includes a host bus adaptor to communicate with an external host via a first interface and to communicate internally via a second interface is provided. The data transfer method may include issuing a write command and a read command to the host bus adaptor; performing a read direct memory access operation using the first interface in response to the write command and simultaneously performing a write direct memory access operation using the second interface in response to the read command; and generating frame information structure (FIS) sequences according to the second interface in response to the issued write command and the issued read command. The first interface may perform a full duplex data transfer and the second interface may perform a half-duplex data transfer.