Host Bus Logic for System Bus Transaction Error Recovery
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Solution Overview
Problem
Computer system devices face challenges in handling errors during input/output operations across different system buses, requiring specific logic for each bus type and leading to potential stalling due to limited transaction tracking capabilities.
Innovation Solution
A meta interface and host bus logic that translates device semantics to system bus semantics, allowing devices to operate across multiple system buses without modification, with reusable operation identifiers and error handling mechanisms to prevent ghost data issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a device includes built-in logic for detecting and handling errors for every type of system bus, then error handling capability is improved, but device complexity increases
Solution Approach 1:
The patent introduces a host bus logic layer as an intermediary between the device and the system bus. This mediator handles all bus-specific error detection and handling logic, allowing the device to remain architecture-agnostic while still achieving reliable error handling across different bus types (PCIe, HT, etc.).
Solution Approach 2:
The device is designed with universal operation identifiers and a standardized interface that works across multiple different system bus architectures. The host bus logic provides the specialized error handling for each bus type, making the device itself universal while maintaining high reliability through bus-specific error management.
2Measurement precision
If a device tracks transactions for every type of system bus, then transaction tracking accuracy is improved, but device complexity increases
Solution Approach 1:
The host bus logic serves as the intermediary that tracks transactions specific to each bus architecture. The device simply issues operations with operation identifiers and relies on the host bus logic to manage the complex transaction tracking, achieving accurate measurement without increasing device complexity.
3Productivity
If split transactions are enabled for read operations, then bus access efficiency is improved, but error recovery complexity increases
Solution Approach 1:
The host bus logic acts as the mediator that manages split transaction error recovery. When errors occur during split read operations, the host bus logic handles the recovery process by mapping operation identifiers to transaction identifiers and coordinating error handling across multiple transactions, thereby maintaining bus access efficiency without burdening the device with complex recovery logic.
4Adaptability or versatility
If the device can operate with multiple different system buses without modification, then adaptability is improved, but error handling capability may worsen
Solution Approach 1:
The host bus logic is the intermediary that provides bus-specific error handling for each system bus type. The device maintains multi-bus compatibility through standardized operation identifiers and interfaces, while the host bus logic ensures reliable error handling by implementing architecture-specific error detection and recovery mechanisms.
Solution Approach 2:
The device achieves universality across multiple bus architectures through a standardized interface and operation identifier system. The host bus logic provides the specialized error handling for each bus type, allowing the device to be universally applicable while maintaining high reliability through bus-specific error management.
Data Source
AI summary
A method and apparatus for recovering from errors occurring during system bus transactions. An input/output device such as a network interface unit (NIU) issues read and write operations across a meta interface coupling the device to host bus (glue) logic. The host bus logic translates the operations into system bus transactions. The device maintains a set of reusable identifiers for identifying the operations, and a table maintained by the device or the host bus logic maps the operation identifiers to transaction identifiers identifying the system bus transactions spawned to perform the operations. If a bus transaction encounters an unrecoverable error, the host bus logic reports the error to the device and drops any further data received from other bus transactions performed for the same operation. The device marks the operation's identifier as dirty, to prevent its reuse. The operation identifier may be reused after software clears the error condition.