Host-Cached Map Data for Nonvolatile Storage Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The removal of a high-capacity buffer memory, such as DRAM, from storage devices leads to decreased operating speeds due to insufficient capacity in the controller's buffer memory for managing metadata, resulting in longer response times for write and read requests.
Innovation Solution
The storage device sends map data to the host device, allowing the host to cache this data, enabling it to send read requests with physical addresses, thereby bypassing the need for the controller to perform address translation and reducing the time required for operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a high-capacity buffer memory like DRAM is removed from the storage device, then manufacturing costs are reduced, but the operating speed decreases due to insufficient buffer memory capacity for managing metadata
Solution Approach 1:
The patent extracts the map data from the storage device's buffer memory and relocates it to the host device's memory. This removes the need for the storage device to maintain large buffer memory capacity, reducing manufacturing costs while preserving fast access capabilities at the host side.
Solution Approach 2:
The patent introduces an intermediary mechanism where the host device acts as a buffer for map data. The host device's memory serves as an intermediate storage that caches the mapping information, allowing the storage device to operate with minimal buffer memory while maintaining translation capabilities through host-side caching.
2Device complexity
If the buffer memory capacity in the controller is small, then device complexity is reduced, but the response time increases when map data needs to be loaded from nonvolatile memory
Solution Approach 1:
The patent implements preliminary action by having the host device load and cache map data in advance before actual data transfer operations occur. This pre-caching of mapping information eliminates the need for time-consuming memory operations during critical data transfer paths, reducing response time while keeping the storage device's buffer memory small.
3Ease of operation
If address translation is performed by the controller for every read request, then data access is simplified, but operating speed decreases due to additional translation time
Solution Approach 1:
The patent merges the address translation function with the data caching function by having the host device perform both operations simultaneously. The host device caches map data and uses it for translation, combining what were previously separate operations into a unified process that eliminates redundant translation steps and improves operating speed.
Data Source
AI summary
An operating method of a storage device that includes a nonvolatile memory device and a controller configured to control the nonvolatile memory device includes sending map data from the storage device to a host device, the map data mapping one or more of a plurality of physical addresses of the nonvolatile memory device to one or more of a plurality of logical addresses of the host device; receiving, at the storage device, a read request from the host device; if the read request includes a physical address, reading data from the nonvolatile memory device based on the included physical address; and if the read request does not include a physical address, translating a logical address of the read request into a first physical address, and reading data from the nonvolatile memory device based on the translated first physical address.