Host Clock Delay Range Extension via Edge Selection
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Solution Overview
Problem
The existing delay elements in communication interfaces between host systems and storage systems have limited configurable delay, leading to challenges in aligning data for sampling, particularly during high-speed operations where propagation delays can change due to operating conditions such as temperature and voltage fluctuations.
Innovation Solution
The implementation of a host input circuit with a delay circuit and a sampling circuit that applies a configurable delay to either the input signal or the clock signal, and a selection circuit to align the sampled data with a subsequent clock edge, extending the effective delay range beyond the limitations of traditional delay elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional delay elements are used in communication interfaces, then device complexity is reduced, but the configurable delay range is limited and cannot accommodate propagation delay changes during high-speed operations
Solution Approach 1:
The delay adjustment function is segmented into two independent parts: a traditional delay element providing fine-grained delay within a limited range, and a clock edge selection mechanism providing coarse-grained delay extension by selecting different clock edges. This segmentation allows the system to achieve a wide effective delay range without proportionally increasing complexity of each individual component.
Solution Approach 2:
The clock edge selection circuit serves multiple functions: it extends the delay range, maintains synchronization during high-speed operations, and works cooperatively with the traditional delay element. By making the clock edge selection mechanism multi-functional, the patent avoids adding dedicated complexity solely for delay extension while simultaneously improving adaptability.
2Reliability
If the delay range is extended to accommodate propagation delay changes, then synchronization reliability is improved, but the number of delay taps and circuit complexity increase
Solution Approach 1:
Instead of providing a static, continuously increasing number of delay taps to cover the entire delay range, the patent implements a dynamic solution where the clock edge selection is adjusted based on operating conditions such as speed mode and propagation delay changes. This dynamic approach maintains synchronization reliability while avoiding the need for a large fixed number of delay taps.
Solution Approach 2:
The system uses its own clock signal edges as a resource to extend delay functionality. By selecting different clock edges (e.g., first edge, second edge, third edge) from the existing clock signal, the system achieves delay extension without requiring external additional components or a proportionally increased number of delay taps.
3Adaptability or versatility
If more delay taps are added to extend delay range, then delay coverage is improved, but manufacturing precision requirements and device complexity increase
Solution Approach 1:
The delay coverage requirement is segmented between the traditional delay element (handling fine-grained delay with limited taps) and the clock edge selection mechanism (handling coarse-grained delay extension). This segmentation allows each component to operate within its optimized precision range, reducing overall manufacturing precision requirements compared to a single delay element covering the entire range.
Data Source
AI summary
Devices and techniques are disclosed herein to extend a range of an effective delay of a delay circuit having a configurable delay limited to a first range of delay values with respect to a first edge of a clock signal. A selection circuit can selectively apply the configurable delay to a subsequent, second edge of the clock signal to extend the range of the effective delay of the delay circuit beyond the first range of delay values.