Host Clock Phase Shifting for Level-Shifter Timing Skew
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Solution Overview
Problem
The presence of level shifters in host and storage devices causes signal delay and skewing, leading to communication failures between the host and storage devices when operating at different voltages, affecting data transmission.
Innovation Solution
A host interface with a phase shifter that modulates the clock phase based on a response or feedback clock from a level shifter, using a phase shift detector and control logic to synchronize data communication and prevent signal delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If level shifters are used to enable communication between host and storage device operating at different voltages, then voltage level compatibility is improved, but signal delay and skewing increase causing communication failures
Solution Approach 1:
The patent applies preliminary action by detecting the phase shift caused by level shifters in advance and compensating for it before data communication occurs. The host interface detects the phase shift between the clock signal and the feedback clock signal, then adjusts the sampling timing accordingly to compensate for the delay introduced by level shifters, ensuring reliable data communication.
Solution Approach 2:
The patent uses feedback by utilizing the feedback clock signal from the storage device to detect and measure the phase shift introduced by level shifters. This feedback mechanism allows the host interface to continuously monitor and adjust for timing deviations, maintaining synchronization and communication reliability despite the presence of level shifters.
2Stability of the object's composition
If level shifters are inserted in the communication path between host and device, then voltage domain isolation is improved, but signal transmission time increases causing data loss
Solution Approach 1:
The feedback clock signal provides real-time information about the actual transmission time through level shifters. By comparing the original clock signal with the feedback clock signal, the system measures the time delay and compensates for it by adjusting the sampling timing, thus eliminating the negative impact of extended transmission time while maintaining voltage domain isolation.
Solution Approach 2:
The patent changes the timing parameter of data sampling to compensate for the time delay introduced by level shifters. By dynamically adjusting when data is sampled based on the detected phase shift, the system offsets the additional transmission time and prevents data loss while preserving the benefits of voltage domain isolation.
3Measurement precision
If phase shift compensation is implemented using feedback clock, then communication accuracy is improved, but device complexity increases
Solution Approach 1:
The host interface is designed with multi-functionality by combining the data communication function with the phase shift detection and compensation function. The same interface circuitry that handles data transmission also detects the feedback clock signal and performs timing adjustment, eliminating the need for separate dedicated compensation circuits and reducing overall device complexity.
Solution Approach 2:
The patent merges the clock detection function with the data sampling function into a single integrated process. The phase shift detection and timing compensation are combined with the existing data communication protocol, allowing the system to achieve high communication accuracy without adding separate complex compensation circuits.
Data Source
AI summary
A host interface includes; a phase shift detector, a phases shifter, and control logic controlling operation of the phase shift detector and the phase shifter. The host interface sends a command and a clock to a device, receives a response from the device, communicates data to the device synchronously with the clock, and samples data received from the device synchronously with a modulated clock. The phase shift detector provides a shift value based on the response, and the phase shifter modulates a phase of the clock based on the shift value to generate the modulated clock.