Host Device High-Speed Clock Switching for Power Reduction

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Solution Overview

Problem

The existing MIPI standard for high-speed clock switching in host devices is not optimal as it relies on pre-configured time periods, which may not suit varying peripheral conditions, leading to unnecessary power consumption and inefficiency.

Innovation Solution

A method and system for dynamically switching the high-speed clock based on the status of the host and peripheral devices during data transmission and reception, using additional configuration registers to adaptively turn on and off the clock, rather than relying on pre-defined time periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If pre-configured time periods are used for clock switching, then the system is simple to implement, but power consumption increases due to unnecessary clock activity

Engineering Contradiction:
Improveease of implementationVSAvoidpower consumption
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent applies dynamics by transitioning from static pre-configured time periods to dynamic clock switching based on real-time data transmission status. The host device continuously monitors whether data transmission is occurring and adjusts clock switching accordingly, making the system adaptive to varying operational conditions rather than relying on fixed time parameters.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback mechanisms where the host device monitors the actual data transmission status and uses this information to control clock switching. The system receives feedback about whether data is being transmitted and adjusts the clock state (on/off) based on this feedback, creating a closed-loop control system that optimizes power consumption.

Inventive Principle:
Principle #23Feedback

2Ease of operation

If pre-configured time periods are used for clock switching, then the system is easy to operate, but transmission efficiency decreases due to suboptimal clock timing

Engineering Contradiction:
Improveease of operationVSAvoidtransmission efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent enables the system to self-adjust clock switching timing by automatically monitoring its own data transmission status. The host device independently determines when to switch the clock on or off based on real-time detection of data transmission activity, eliminating the need for external configuration or manual timing adjustments while optimizing transmission efficiency.

Inventive Principle:
Principle #25Self-service

3Reliability

If the clock remains active for pre-configured time periods, then peripheral devices have sufficient time to process data, but power dissipation increases

Engineering Contradiction:
Improvedata processing reliabilityVSAvoidpower dissipation
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent maintains continuous useful action by keeping the clock active only during actual data transmission periods and immediately switching it off when transmission stops. This ensures the clock is continuously performing its useful function of supporting data transmission when needed, while avoiding continuous operation that would waste energy during idle periods.

Inventive Principle:
Principle #20Continuity of useful action

4Loss of energy

If the clock is switched off immediately after data transmission, then power consumption is minimized, but peripheral devices may not complete processing

Engineering Contradiction:
Improvepower consumptionVSAvoiddata processing completion
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent applies preliminary action by monitoring data transmission status and preparing for clock switching in advance. The host device detects the cessation of data transmission and switches off the clock accordingly, ensuring that the clock remains on for the exact duration needed for data transmission and processing without extending into unnecessary idle periods.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3163460B1System and method for dynamically switching high-speed clock of a host device
Publication Date: 2019.05.29 WIPRO LTD
  • EP3163460B1 patent drawingFigure 1
  • EP3163460B1 patent drawingFigure 2
  • EP3163460B1 patent drawingFigure 3

AI summary

This disclosure relates generally to a host-peripheral interface, and more particularly to system and method for dynamically switching a high-speed clock of a host device. In one embodiment, a method is provided for dynamically switching a high-speed clock of a host device. The method comprises determining a status of the host device and a peripheral device coupled to the host device with respect to a transmission and a reception of high-speed data respectively, and switching the high-speed clock between the host device and the peripheral device based on the status.