Host Communication Circuit Bidirectional Single Wire Modulation

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Solution Overview

Problem

Current communication systems using single signal wires are limited to unidirectional data transmission, and bidirectional communication over a single signal wire is inefficient due to mutual interference between voltage and current modulation techniques.

Innovation Solution

Implementing a communication concept that uses both current and voltage modulation on a single signal wire, where voltage modulation occurs during a short period of the clock cycle and current modulation during the remaining period, minimizing mutual influence through careful timing and signal forms such as sawtooth or peak pulses, allowing for efficient bidirectional data transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If bidirectional communication is implemented over a single signal wire using both voltage and current modulation, then communication versatility is improved, but mutual interference between modulation techniques increases

Engineering Contradiction:
Improvebidirectional communication capabilityVSAvoidmutual interference between modulation techniques
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The clock cycle is segmented into two distinct periods: a first period for voltage modulation and a second period for current modulation. This temporal segmentation allows each modulation technique to operate independently without mutual interference, while still achieving bidirectional communication over the single signal wire.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The communication system uses periodic voltage and current modulation within clock cycles to transmit data bidirectionally. By alternating between voltage modulation in the first period and current modulation in the second period, the system achieves continuous bidirectional communication while minimizing interference through regular periodic separation.

Inventive Principle:
Principle #19Periodic action

2Reliability

If voltage modulation uses significant voltage changes to ensure reliable transmission, then signal reliability is improved, but current influence on the signal wire increases

Engineering Contradiction:
Improvesignal transmission reliabilityVSAvoidcurrent influence on signal wire
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The clock cycle is divided into a first period for voltage modulation and a second period for current modulation. During the first period, significant voltage changes are applied for reliable voltage modulation without concurrent current modulation interference. During the second period, current modulation occurs without voltage changes, eliminating the harmful interaction between the two modulation techniques.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system periodically alternates between voltage modulation and current modulation within clock cycles. This periodic separation ensures that when significant voltage changes occur for reliable transmission, current modulation is suspended, and when current modulation occurs, voltage remains constant, thereby eliminating mutual interference while maintaining transmission reliability.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables efficient bidirectional communication over a single signal wire by minimizing interference between voltage and current modulation, allowing for reliable clock and data transmission with reduced current influence on the signal wire, even with parasitic capacitances.

Implementation Method 1

The host communication circuit is configured to perform a voltage modulation on the signal wire by generating a voltage modulated signal based on a reference clock signal

Methodology Applied
Scientific EffectVoltage modulation: Phase Modulation

Implementation Method 2

the client communication circuit is configured to perform a current modulation on the signal wire by generating a current modulated signal

Methodology Applied
Scientific EffectCurrent modulation: Phase Modulation

Implementation Method 3

The host communication circuit is further configured to demodulate a current modulated signal received via the signal wire from a connected client communication circuit

Methodology Applied
Scientific EffectCurrent modulation detection: Electrical Impedance Tomography

Data Source

PatentEP2793424B1Host communication circuit, communication system and communication method
Publication Date: 2021.01.27 AUSTRIAMICROSYSTEMS AG
  • EP2793424B1 patent drawingFigure 1~2B
  • EP2793424B1 patent drawingFigure 3
  • EP2793424B1 patent drawingFigure 4A~4B

AI summary

A communication system comprises a host communication circuit (HCC) and a client communication circuit (PCC), which are connected to each other by means of a single signal wire (DEN). The host communication circuit (HCC) generates a voltage modulated signal (VDEN) on the signal wire (DEN) based on a reference clock signal (SYNCLK), which in each clock cycle has a first period with a significant voltage change based on a clock edge of the reference clock signal (SYNCLK), and a second period with a basically constant voltage variation. The host communication circuit (HCC) further can demodulate a current modulated signal (IDEN) received via the signal wire (DEN) from the client communication circuit (PCC). The client communication circuit (PCC) is configured to detect the significant voltage change in order to generate respective sync pulses in a sync signal, which is used to generate a client clock signal (TXCLK). A current modulation is performed by the client communication circuit (PCC) based on the data to be transmitted a predetermined settling time after one of the sync pulses until the respective following sync pulse.