Host-Configurable Error Protection for Memory Subsystems

Solution Overview

Problem

Existing memory systems face inefficiencies in error protection configurations, as they often implement the same configuration for all data types, leading to excessive resource consumption and latency issues for certain types of data, negatively impacting performance.

Innovation Solution

A host system dynamically configures different error protection configurations for subsets of logical addresses based on the type of data, allowing the memory system to tailor its error protection strategies for various data types, thereby optimizing resource usage and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the same error protection configuration is implemented for all data types, then reliability is improved, but resource consumption increases and latency increases for certain data types

Engineering Contradiction:

Improveerror protectionVSAvoidresource consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by implementing different error protection configurations for different logical address subsets based on data type. Instead of uniformly applying the same error protection to all data, the system tailors the protection level to the specific requirements of each data type (e.g., higher protection for critical data, lower protection for non-critical data), thereby reducing overall resource consumption while maintaining necessary reliability.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the logical address space into multiple subsets, each associated with different data types. This segmentation allows the system to apply customized error protection configurations to each subset independently, enabling optimized resource allocation and reduced latency for time-sensitive data while maintaining high reliability for critical data.

Inventive Principle:

Principle #1Segmentation

2Reliability

If the same error protection configuration is implemented for all data types, then reliability is improved, but latency increases for certain data types

Engineering Contradiction:

Improveerror protectionVSAvoidlatency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by implementing different error protection configurations for different logical address subsets based on data type. Instead of uniformly applying the same error protection to all data, the system tailors the protection level to the specific requirements of each data type (e.g., higher protection for critical data, lower protection for non-critical data), thereby reducing overall resource consumption while maintaining necessary reliability.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements dynamic error protection configuration where the protection level can be adjusted based on the data type and operational requirements. This dynamic approach allows the system to reduce protection overhead for time-sensitive operations, thereby reducing latency while maintaining appropriate reliability levels.

Inventive Principle:

Principle #15Dynamics

3Reliability

If stronger error protection is applied to all data, then reliability is improved, but resource consumption increases

Engineering Contradiction:

Improveerror protectionVSAvoidmemory resources

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by implementing different error protection configurations for different logical address subsets based on data type. Instead of uniformly applying the same error protection to all data, the system tailors the protection level to the specific requirements of each data type (e.g., higher protection for critical data, lower protection for non-critical data), thereby reducing overall resource consumption while maintaining necessary reliability.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the error protection parameters (such as parity bits, ECC codes, or redundancy levels) based on the data type and logical address subset. This parameter adjustment allows the system to use stronger protection where needed and weaker protection where sufficient, optimizing the balance between reliability and resource consumption.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11797380B2Host-configurable error protection

Publication Date: 2023.10.24 MICRON TECHNOLOGY INC

AI summary

Methods, systems, and devices for host-configurable error protection are described. A host system may receive an indication of a set of logical addresses supported by the memory system and available for use by the host system. The host system may divide the set of logical addresses into subsets of logical addresses. Each subset of logical addresses may be associated with a different type of data. The host system may determine an error protection configuration for a subset of logical addresses based at least in part on the type of data associated with the subset of logical addresses. The host system may then send to the memory system an indication of the subset of logical addresses and an indication of the error protection configuration for the subset of logical addresses.