Host Controlled Data Buffer Address Sequencing
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Solution Overview
Problem
Current memory systems face performance limitations due to bandwidth constraints on communication links between the Host, memory control circuits, data buffer circuits, and memory devices, affecting the efficiency of data storage and retrieval operations.
Innovation Solution
A memory system architecture that includes a memory control circuit, data buffer circuits, and communication links between the Host, memory devices, and memory control circuits, where data buffer circuits receive store data tags from the Host and automatically move data into their buffers, and the memory control circuit processes commands to optimize data storage and retrieval operations by prioritizing fetch operations and scheduling store operations for optimal system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the memory control circuit sends control information (store data tags) to data buffer circuits for each data storage operation, then data storage accuracy is improved, but communication link bandwidth is consumed
Solution Approach 1:
The host sends store data tags to data buffer circuits in advance before data arrives. The data buffer circuits receive and store these tags beforehand, so when data is received, the destination addresses are already prepared and stored in the data buffer circuits, eliminating the need for repeated control information transmission.
Solution Approach 2:
The store data tag is copied from the host to the data buffer circuit in advance. This copy of the tag remains in the data buffer circuit, serving as a persistent address reference that eliminates the need for the host to resend the same control information for each subsequent data transmission to the same location.
2Reliability
If the memory control circuit processes and schedules all store operations, then data storage reliability is improved, but system performance and bandwidth efficiency deteriorate
Solution Approach 1:
Data buffer circuits autonomously use the store data tags received from the host to determine where to store incoming data without requiring continuous control from the memory control circuit. Each data buffer circuit independently manages its own data reception and storage operations based on pre-received tags, reducing the processing burden on the memory control circuit.
Solution Approach 2:
The centralized control function is segmented and distributed to individual data buffer circuits. Each data buffer circuit independently handles data storage operations using its stored tags, distributing the control workload across multiple independent units rather than concentrating it all in the memory control circuit.
3Measurement precision
If control information is sent frequently to maintain data buffer synchronization, then data retrieval accuracy is improved, but communication link bandwidth is reduced
Solution Approach 1:
Store data tags are sent to data buffer circuits in advance before data transmission begins. This preliminary action ensures that all address information is prepared beforehand, eliminating the need for frequent synchronization control information during data transfer operations.
Solution Approach 2:
The system maintains continuous data transfer operations without interruption for control information exchange. Since tags are pre-sent and stored, the data buffer circuits can continuously receive and store data without pausing to request or process control information, maximizing the continuity of useful data transfer action.
Data Source
AI summary
One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one aspect, the data buffer circuit receives a next to be used store data tag from a Host wherein the store data tag specifies the data buffer location in the data buffer circuit to store data, and in response to receiving store data from the Host, moves the data received at the data buffer circuit into the data buffer pointed to by the previously received store data tag.