Host Device Clock Switching for Boot Data Transfer Efficiency
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Solution Overview
Problem
Existing data transfer systems experience reduced transfer efficiency during boot data transfer due to significant overhead from interface voltage switching, as seen in PTL 2, which affects high-speed interface processing.
Innovation Solution
A data transfer system where the host device supplies power and a first clock to the slave device, then drives the command line to a low level, stops the first clock, and switches to a second clock with a different frequency and voltage, allowing the slave device to transmit boot data efficiently without command exchange during the transition, thereby reducing overhead time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interface voltage switching is performed to enable high-speed data transfer, then data transfer speed is improved, but transfer efficiency of boot data is deteriorated due to switching overhead time
Solution Approach 1:
The host device performs preliminary actions by driving the command line to a low level and stopping the first clock before switching to the second clock. This preparation eliminates the need for command exchange during the voltage switching transition, reducing overhead time and improving boot data transfer efficiency while maintaining high-speed transfer capabilities
2Reliability
If command exchange is performed during voltage switching, then interface protocols are maintained, but overhead time increases and transfer efficiency decreases
Solution Approach 1:
The command line is driven to a low level and the first clock is stopped before voltage switching occurs, preparing the interface in advance. This preliminary state setup allows the second clock to be supplied without requiring command exchange during the transition, maintaining protocol reliability while minimizing overhead time
Solution Approach 2:
The system dynamically adjusts the command line state and clock supply based on the voltage switching phase. During the transition from first to second clock, the command line is held at a low level and clock supply is dynamically controlled, allowing seamless voltage switching without command exchange overhead
Data Source
AI summary
A data transfer system includes a slave device, and a host device that is connected to the slave device via at least a power supply line, a clock line, a command line, and a data line. A CMD line is continuously driven to a low level in a period from when the supply of at least a first clock is stopped to when the second clock is supplied (period form timing t5 to timing t6).