Host-Device Flash Translation Layer Segmentation for SSD Write Amplification
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Solution Overview
Problem
Current memory systems with NAND flash technology face challenges in controlling I/O performance due to complex address translation and garbage collection processes, leading to increased memory resources consumption and reduced storage performance, as well as shortened SSD lifetime.
Innovation Solution
A memory system where the role of the flash translation layer is shared between the host and the flash storage device, with the host managing logical addresses and the device determining in-block physical addresses, thereby reducing the frequency of garbage collection and write amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the flash translation layer is fully implemented in the memory system, then address translation and garbage collection can be performed, but memory resource consumption increases and I/O performance deteriorates
Solution Approach 1:
The flash translation layer functionality is segmented and distributed between the host processor and the memory system. The host manages logical-to-physical address translation using its own translation layer, while the memory system handles only the flash-specific translation layer. This segmentation reduces the processing burden on the memory system and improves I/O performance while maintaining address translation capability.
Solution Approach 2:
The address translation functionality is extracted from the memory system and relocated to the host. By removing the FTL from the memory system and implementing it in the host, the patent eliminates the performance bottleneck and resource consumption issues associated with having a complete FTL in the storage device, while still providing the necessary address translation through the host's translation layer.
2Reliability
If the flash translation layer is fully implemented in the memory system, then garbage collection can be performed, but the SSD lifetime is shortened due to increased write amplification
Solution Approach 1:
Garbage collection responsibilities are segmented between the host and memory system. The host's translation layer tracks logical-to-physical address mappings and identifies obsolete data, while the memory system executes garbage collection operations based on host coordination. This segmentation reduces write amplification by enabling more efficient garbage collection that leverages the host's address translation information.
Solution Approach 2:
The host translation layer provides feedback about address translation status and obsolete data identification to the memory system. This feedback mechanism enables the memory system to perform garbage collection more efficiently by having advance knowledge of which data is obsolete, reducing unnecessary write operations and extending SSD lifetime.
3Reliability
If a complete flash translation layer is implemented, then comprehensive address translation can be performed, but device complexity increases
Solution Approach 1:
The complex address translation functionality is extracted from the memory system and implemented in the host. By removing the FTL from the storage device and placing it in the host processor, the patent significantly reduces the complexity of the memory system while maintaining comprehensive address translation capability through the host's translation layer.
Solution Approach 2:
The host processor is utilized to perform address translation functions that would otherwise require dedicated FTL hardware or firmware in the memory system. By leveraging the host's existing processing capabilities and translation layer, the patent eliminates the need for complex dedicated translation infrastructure in the storage device.
Data Source
AI summary
According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller is electrically coupled to the nonvolatile memory. The controller controls the nonvolatile memory. When receiving, from the host, a first command for changing a state of an allocated block to a reallocatable state in a case where a second command that is yet to be executed or being executed involving read of data from the allocated block has been received from the host, the controller changes the state of the allocated block to the reallocatable state after the second command is finished.