Memory Link ECC Using Host and Device-Side Protection Codes

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Solution Overview

Problem

Conventional memory systems face performance and cost issues due to the need for additional memory devices and increased I/O width for error correction codes (ECC), which also result in inefficient use of memory bandwidth and increased power consumption.

Innovation Solution

Incorporating ECC encoding and decoding capabilities within both the host and memory devices, allowing for error detection and correction without requiring additional memory devices, maintaining the existing link configuration and burst length, and utilizing existing signal lines for ECC communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional memory devices are used to store ECC codes, then reliability is improved, but device complexity and cost increase

Engineering Contradiction:
Improvememory link reliabilityVSAvoidmemory device count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies multi-functionality by enabling existing memory devices to serve dual purposes: storing both data and ECC codes. The memory devices that normally store data are configured to also store ECC codes for other memory devices, eliminating the need for dedicated ECC storage resources. This is achieved through the host system's ability to identify which memory devices are operational and dynamically allocate ECC storage capacity among them.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system implements self-service by having operational memory devices generate and store ECC codes for themselves and other operational devices. The memory subsystem autonomously manages error correction without requiring external intervention or additional dedicated components. The host system automatically detects operational devices and configures ECC storage allocation based on current system state.

Inventive Principle:
Principle #25Self-service

2Reliability

If I/O width is increased to accommodate ECC bits, then reliability is improved, but manufacturing precision and PCB area increase

Engineering Contradiction:
Improvememory link reliabilityVSAvoidPCB area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies multi-functionality by enabling existing memory devices to serve dual purposes: storing both data and ECC codes. The memory devices that normally store data are configured to also store ECC codes for other memory devices, eliminating the need for dedicated ECC storage resources. This is achieved through the host system's ability to identify which memory devices are operational and dynamically allocate ECC storage capacity among them.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically changes operational parameters based on detected memory device states. When memory devices are added or removed, the host system recalculates and adjusts the allocation of ECC storage capacity, modifying the operational configuration without hardware changes. This allows flexible adaptation to different system configurations while maintaining error correction functionality.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If additional memory devices are added for ECC, then reliability is improved, but power consumption increases

Engineering Contradiction:
Improvememory subsystem reliabilityVSAvoidmemory power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies multi-functionality by enabling existing memory devices to serve dual purposes: storing both data and ECC codes. The memory devices that normally store data are configured to also store ECC codes for other memory devices, eliminating the need for dedicated ECC storage resources. This is achieved through the host system's ability to identify which memory devices are operational and dynamically allocate ECC storage capacity among them.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system implements self-service by having operational memory devices generate and store ECC codes for themselves and other operational devices. The memory subsystem autonomously manages error correction without requiring external intervention or additional dedicated components. The host system automatically detects operational devices and configures ECC storage allocation based on current system state.

Inventive Principle:
Principle #25Self-service

4Reliability

If I/O width is increased for ECC, then reliability is improved, but memory bandwidth efficiency decreases

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoidmemory bandwidth efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies multi-functionality by enabling existing memory devices to serve dual purposes: storing both data and ECC codes. The memory devices that normally store data are configured to also store ECC codes for other memory devices, eliminating the need for dedicated ECC storage resources. This is achieved through the host system's ability to identify which memory devices are operational and dynamically allocate ECC storage capacity among them.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically changes operational parameters based on detected memory device states. When memory devices are added or removed, the host system recalculates and adjusts the allocation of ECC storage capacity, modifying the operational configuration without hardware changes. This allows flexible adaptation to different system configurations while maintaining error correction functionality.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10331517B2Link error correction in memory system
Publication Date: 2019.06.25 QUALCOMM INC
  • US10331517B2 patent drawing
  • US10331517B2 patent drawing
  • US10331517B2 patent drawing

AI summary

Conventional link error correction techniques in memory subsystems include either widening the I/O width or increasing the burst length. However, both techniques have drawbacks. In one or more aspects, it is proposed to incorporate link error correction in both the host and the memory devices to address the drawbacks associated with the conventional techniques. The proposed memory subsystem is advantageous in that the interface architecture of conventional memory systems can be maintained. Also, the link error correction is capability is provided with the proposed memory subsystem without increasing the I/O width and without increasing the burst length.