Host Device Memory System Parallel Bus Architecture
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Solution Overview
Problem
Current storage devices face challenges in increasing capacity and operating speed, particularly when handling large amounts of data and requiring simultaneous write/read operations, as existing technologies struggle to efficiently utilize multiple storage modules over a single host interface bus without compromising data transmission speed.
Innovation Solution
A host device and memory system architecture that utilizes multiple storage modules connected through a single host interface bus, allowing parallel writing of data to multiple memory units via a shared bus, with each module having its own controller and memory unit, and employing a crossbar switch for efficient data transmission and chip selection, enabling simultaneous operations across multiple storage regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple storage modules are connected through a single host interface bus, then storage device capacity and operating speed are improved, but data transmission efficiency deteriorates due to shared bus contention
Solution Approach 1:
The patent divides the data transmission path into multiple independent channels by connecting each storage module to the host device through separate host interface buses. This segmentation allows parallel data transmission to multiple storage modules simultaneously, eliminating the bottleneck of shared bus contention while maintaining high data transmission speeds. Each storage module operates independently on its own bus, enabling the system to achieve both high capacity and high operating speed.
2Speed
If additional host interface buses are used to connect multiple storage modules, then data transmission speed is improved, but device complexity increases
Solution Approach 1:
Instead of using a single shared bus, the patent segments the bus architecture into multiple independent host interface buses, each dedicated to a specific storage module. This segmentation approach improves data transmission speed by eliminating bus contention while keeping each individual bus simple and manageable. The modular bus architecture allows for scalable expansion without exponentially increasing system complexity.
Solution Approach 2:
The patent transitions from a one-dimensional shared bus topology to a multi-dimensional parallel bus architecture. By adding the dimension of parallelism with multiple independent buses, the system achieves higher data transmission speeds without proportionally increasing complexity, as each bus operates independently and can be managed separately.
3Productivity
If parallel writing to multiple memory units is implemented, then productivity is improved, but control complexity increases
Solution Approach 1:
The patent segments the control function by providing each storage module with its own dedicated module controller. This segmentation allows each controller to independently manage parallel writing operations to its associated memory unit without coordinating with other controllers. The result is improved productivity through parallel operations while avoiding the complexity of inter-controller coordination and synchronization.
Solution Approach 2:
Each storage module with its dedicated module controller operates autonomously, performing self-service for data writing operations. The controllers independently receive data from the host device and write to their respective memory units without requiring coordination or communication with other controllers. This self-service approach maximizes parallel productivity while minimizing control complexity.
Data Source
AI summary
A memory module includes a first storage module including a first module controller and a first memory unit. The first storage module is configured to receive first partial data from a host and write the first partial data to the first memory unit. A second storage module includes a second module controller and a second memory unit. The second storage module is configured to receive second partial data from the host and write the second partial data to the second memory unit. The first storage module and the second storage module are configured to connect to the host through a single host interface bus.