Host DMA Read Path Switching for Lower SSD Read Latency

The patent segments the DMA operation into two distinct paths: a 1-stage DMA path for sequential reads that bypasses the buffer, and a 2-stage DMA path for random reads that uses the buffer. This segmentation allows the system to optimize for speed in sequential operations while maintaining buffering capabilities for random operations, thereby reducing read latency without unnecessarily increasing buffer size for all operations.

The patent implements dynamic path selection based on read request attributes. The controller dynamically determines whether to use the 1-stage or 2-stage DMA path depending on whether the read operation is sequential or random. This dynamic adaptation allows the system to minimize buffer usage for sequential reads (reducing latency) while maintaining full buffering for random reads when needed.

The patent applies local quality by providing different buffering capabilities for different read operation types. The 1-stage DMA path for sequential reads uses minimal or no buffering, while the 2-stage DMA path for random reads utilizes the full buffer. This localized optimization ensures that buffer memory is allocated and used only where it provides actual benefit, reducing overall buffer size requirements while maintaining data buffering capability for operations that need it.

The buffer memory serves multiple functions: it acts as a data staging area for 2-stage DMA operations, provides caching for random reads, and can be bypassed entirely for sequential reads. This multi-functionality allows the buffer to provide reliability benefits when needed without requiring excessive buffer size for all operation types, thereby reducing cost while maintaining buffering capability.

The patent performs preliminary action by pre-determining the read path based on read request attributes before the actual data transfer begins. The controller examines the read request to identify whether it is sequential or random, and accordingly selects the 1-stage or 2-stage DMA path in advance. This preliminary path selection enables the system to optimize for read speed using the 1-stage path for sequential reads without adding buffer management complexity during the actual data transfer phase.

The host DMA manager acts as an intermediary that coordinates between the host controller and the buffer memory. It manages the path selection logic and coordinates data flow between the non-volatile memory interface, buffer, and host interface. This intermediary simplifies buffer management by centralizing the path selection and data routing logic, allowing the 1-stage DMA path to achieve high read speed without imposing complexity on the buffer management subsystem.