Host DQ Remapping for Memory Swizzle Error Correction
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Solution Overview
Problem
Memory module designs that prioritize routing efficiency and signal integrity often re-map data terminals in a most-significant-bit to least-significant-bit order, which compromises the host's ability to perform effective error correction, reducing reliability and robustness.
Innovation Solution
Implementing DQ mapping circuits in memory packages or hosts to rearrange data terminals, circumventing the swizzle mapping, thereby maintaining data order integrity and facilitating robust error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data terminals are re-mapped in MSB to LSB order for routing efficiency and signal integrity, then routing efficiency and signal integrity are improved, but the host's ability to perform error correction operations is reduced
Solution Approach 1:
The patent applies inversion by implementing a DQ mapping circuit that reverses the swizzle mapping applied by the memory module. Instead of accepting the re-ordered data terminals and trying to work around the limitation, the host controller actively unmaps the data in reverse order, transforming the data terminal order from MSB-to-LSB back to the original configuration, thereby restoring full error correction capability without changing the memory module's internal routing
Solution Approach 2:
The DQ mapping circuit acts as an intermediary between the memory module's re-mapped data terminals and the host's error correction operations. This intermediary component performs the unmapping operation, translating the re-ordered data into a format suitable for error correction while allowing both the memory module's routing optimization and the host's error correction to coexist
2Productivity
If data terminals are re-mapped for routing efficiency, then routing efficiency is improved, but reliability and robustness of the memory module are reduced
Solution Approach 1:
The patent resolves this contradiction by inverting the data terminal order through the DQ mapping circuit in the host controller. This allows the memory module to maintain its optimized MSB-to-LSB routing configuration for improved routing efficiency, while the host controller simultaneously performs the reverse mapping to restore the original data order, thereby maintaining both routing efficiency and error correction robustness
3Reliability
If data terminals are re-mapped in MSB to LSB order, then signal integrity is improved, but the host's ability to perform error correction operations is reduced
Solution Approach 1:
The DQ mapping circuit serves as an intermediary that receives the signal-integrity-optimized re-mapped data from the memory module and transforms it into the appropriate format for error correction operations. This intermediary unmaps the data terminals, allowing the host to perform error correction operations effectively while the memory module maintains its signal integrity through optimized routing
Data Source
AI summary
An exemplary host includes a data mapping decoder configured to decode a swizzle mapping signal received from a memory module to provide a data mapping setting, a data input/output circuit configured to receive a plurality of data bits from the memory module via a data bus, and a data adjustment circuit configured to re-arrange an order of the plurality of data bits based on the data mapping setting to provide a plurality of adjusted data bits.