Host and Extension Box Architecture for AI Expandability
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Solution Overview
Problem
Current dedicated hardware for artificial intelligence (AI) is insufficient for efficient inference and learning operations, as it relies on repurposed components like CPUs, GPUs, FPGAs, and ASICs, which limit performance and expandability.
Innovation Solution
An electronic device architecture featuring a host box with a processor, motherboard, and power supply, along with independent extension boxes that include their own motherboards, power supplies, controllers, and accelerators, forming a tree structure to optimize data processing and expandability, allowing for decentralized AI operations without relying on the host memory for data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dedicated hardware for AI is implemented using repurposed components like CPU, GPU, FPGA, and ASIC, then the device can perform AI operations, but the performance and expandability are limited
Solution Approach 1:
The system is divided into a host box and multiple extension boxes, where each extension box contains independent AI accelerators and can be added or removed independently. This segmentation allows the system to scale AI processing capacity without redesigning the entire hardware architecture, directly addressing the limited expandability issue while maintaining manageable complexity through modular design.
2Productivity
If the host processor controls all operations, then the system is easier to manage, but the host processor becomes a bottleneck for AI processing performance
Solution Approach 1:
A bridge circuit is introduced as an intermediary between the host box and extension boxes. The bridge circuit handles data transfer and communication protocols, allowing the host processor to manage multiple AI accelerators without being directly involved in every data transfer operation. This intermediary layer offloads communication overhead from the host processor, improving AI processing throughput while maintaining centralized management capability.
3Speed
If data is transferred through host memory, then the system architecture is simpler, but the data transfer speed and processing efficiency are reduced
Solution Approach 1:
The data path is segmented into direct connection routes between extension boxes and the host box, bypassing the host memory for AI-related data transfers. This segmentation creates dedicated high-speed data pathways for AI workloads, enabling faster data transfer between accelerators and the host processor without increasing overall system complexity, as the direct paths utilize existing interface circuits.
Data Source
AI summary
An electronic device includes: a host box comprising a host processor configured to control an operation of the electronic device, a host motherboard in which the host processor is disposed, and a host power supply unit (PSU) configured to supply power to a component connected to the host motherboard; and one or more extension boxes controlled by the host box, wherein each of the one or more extension boxes comprises an extension motherboard independent of the host box, and an extension PSU independent of the host box and configured to supply power to a component connected to the extension motherboard.