Host-Flash L2P Table Sync for Fewer Cache Misses
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Solution Overview
Problem
The synchronization between logical to physical (L2P) lookup tables stored in a host device and a memory system often becomes out of sync, leading to L2P cache misses and reduced read throughput.
Innovation Solution
A memory controller updates a first L2P table on a memory module and sets a bit indicating the update, then transmits an indication to the host device, which updates its corresponding L2P table accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory system updates its L2P table independently, then the memory system can maintain its data mapping efficiently, but the host device L2P table becomes out of sync leading to cache misses
Solution Approach 1:
The memory system sends an interrupt signal to the host device when the L2P table is updated, providing feedback that triggers the host to synchronize its L2P table with the memory system's L2P table, thereby maintaining consistency without continuous polling
Solution Approach 2:
An interrupt mechanism acts as an intermediary between the memory system and host device, conveying update notifications from the memory system to the host device, enabling asynchronous synchronization
2Reliability
If the host device continuously checks for L2P table updates, then synchronization can be maintained, but read throughput decreases due to frequent checks
Solution Approach 1:
Instead of continuous checking, the system uses periodic interrupt-based notifications where the host device only checks for updates when an interrupt signal is received, reducing unnecessary checks and improving read throughput while maintaining synchronization
Solution Approach 2:
The memory system automatically generates and sends interrupt notifications to the host device when updates occur, eliminating the need for the host device to continuously poll for changes, thereby reducing overhead and improving throughput
Data Source
AI summary
This disclosure provides systems, methods, and devices for memory systems that support updating a logical to physical (L2P) table of a host device in accordance with one or more updates to a corresponding L2P table of a memory system. In a first aspect, a method of accessing data in a flash memory system includes a host memory controller receiving an indication of an update to a first logical to physical (L2P) table stored on a first memory of a memory system and updating a second L2P table stored on a second memory of the host device in accordance with the update to the first L2P table. Other aspects and features are also claimed and described.