Host Frame Parser for On-the-fly MPA Marker Insertion
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Solution Overview
Problem
Current RDMA-enabled network adapters face challenges in efficiently handling TCP/IP operations over Ethernet fabrics, particularly in inserting and removing MPA markers, performing speculative CRC calculations, and managing message completions with acceptable latency, especially at high speeds like 10 Gb/sec, due to limitations in TCP's stream-oriented nature and lack of inherent message boundary demarcation capabilities.
Innovation Solution
The implementation of a host frame parser and protocol engine apparatus that enables on-the-fly insertion and removal of MPA markers, performs speculative MPA CRC calculations, and tracks message completions efficiently, allowing for direct memory access operations between a host server and a network adapter, thereby bypassing the need for additional buffers and reducing CPU overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional TCP/IP operations are performed over Ethernet fabrics, then data transfer reliability is maintained, but latency increases and throughput is reduced due to CPU overhead and lack of efficient marker handling
Solution Approach 1:
The patent extracts marker insertion and removal operations from the main data processing path by implementing dedicated host frame parser and protocol engine components that handle these operations independently. This allows the main data transfer to proceed without waiting for marker processing, reducing latency while maintaining throughput.
Solution Approach 2:
The patent performs speculative CRC calculations in advance before data transfer completes, and pre-positions markers for insertion/removal operations. This preliminary action eliminates the need for synchronous processing during data transfer, reducing latency and improving throughput.
2Productivity
If MPA markers are inserted and removed in traditional manner, then message boundary demarcation is achieved, but CPU overhead increases and processing efficiency decreases
Solution Approach 1:
The patent replaces CPU-based mechanical marker processing with a protocol engine that handles marker insertion and removal automatically. This substitution reduces CPU overhead while maintaining the necessary message boundary demarcation functionality.
Solution Approach 2:
The host frame parser and protocol engine perform self-service by automatically managing their own marker insertion and removal operations without requiring external CPU intervention. This self-service mechanism reduces CPU overhead and improves processing efficiency.
3Ease of operation
If additional buffers are used for marker handling, then marker insertion and removal can be performed, but device complexity increases and memory resources are consumed
Solution Approach 1:
The patent extracts the buffer management function from the main system by implementing a dedicated protocol engine that handles marker operations independently. This extraction simplifies the overall system architecture while maintaining marker handling capability.
Solution Approach 2:
The host frame parser and protocol engine perform multiple functions including marker insertion, marker removal, and CRC calculations within a single integrated component. This multi-functionality eliminates the need for separate buffers and reduces device complexity.
4Reliability
If speculative CRC calculations are performed, then error checking is improved, but processing time increases if not optimized
Solution Approach 1:
The patent performs speculative CRC calculations in advance during data reception before the data is fully processed. This preliminary action allows error checking to be completed without delaying the main data transfer, improving reliability while minimizing processing time impact.
Solution Approach 2:
The patent implements continuous CRC calculation during the data reception stream, rather than performing discrete CRC checks at specific points. This continuous approach maintains processing efficiency while ensuring comprehensive error checking.
Data Source
AI summary
An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.