Host Flash Translation Layer for SSD Metadata Adaptation

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Solution Overview

Problem

Updating storage architectures to accommodate different designs or combinations of solid-state memories poses logistical and metadata management challenges.

Innovation Solution

Implementing a direct-mapped flash storage system where the operating system directly addresses data blocks without translation by storage controllers, offloading device management responsibilities to storage array controllers, and utilizing non-volatile RAM for quick data buffering and proactive data rebuilding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If storage architectures are updated to accommodate different designs or combinations of solid-state memories, then adaptability is improved, but device complexity and metadata management challenges increase

Engineering Contradiction:
ImproveadaptabilityVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system divides storage management into separate components: the flash translation layer is separated from the solid-state drives themselves and placed in the host system. This segmentation allows each SSD to remain simple while the collective system achieves adaptability through the external translation layer that can accommodate different flash memory types and configurations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a flash translation layer as an intermediary component between the host system and multiple solid-state drives. This translation layer handles the complexity of different flash memory architectures, translations, and metadata management, thereby enabling adaptability without increasing the complexity of individual drives.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If storage controllers perform translation operations, then adaptability is improved, but write operations increase and efficiency decreases

Engineering Contradiction:
ImproveadaptabilityVSAvoidefficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent extracts the translation function from the storage controllers within the solid-state drives and relocates it to a flash translation layer in the host system. This extraction eliminates unnecessary write operations that would otherwise be performed by each drive's controller, thereby improving write efficiency while maintaining adaptability through the centralized translation capability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Speed

If data is buffered in volatile memory, then speed is improved, but reliability decreases due to data loss on power failure

Engineering Contradiction:
ImprovespeedVSAvoidreliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system proactively rebuilds data from parity information to non-volatile storage before power failures can occur. This preliminary action ensures that data is safely stored in reliable non-volatile memory while still allowing fast volatile memory buffering for active operations, thus maintaining both speed and reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements proactive data rebuilding mechanisms that create a safety buffer against power failures. By continuously maintaining updated copies of data in non-volatile storage through parity-based reconstruction, the system cushions against potential data loss while preserving the performance benefits of volatile memory buffering.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12511239B2Updates for flash translation layer
Publication Date: 2025.12.30 PURE STORAGE INC
  • US12511239B2 patent drawing
  • US12511239B2 patent drawing
  • US12511239B2 patent drawing

AI summary

A method of operating a storage system is provided. The method includes executing an operating system on one or more processors of a compute device that is coupled to one or more solid-state drives and executing a file system on the one or more processors of the compute device. The method includes configuring the compute device with one or more replaceable plug-ins that are specific to the one or more solid-state drives, and executing a flash translation layer on the one or more processors of the compute device, with assistance through the one or more replaceable plug-ins for reading and writing the one or more solid-state drives.