Host Interconnection Device for X86 SoC Memory Latency Reduction
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Solution Overview
Problem
Current X86 system on a chip (SoC) interconnection architectures, such as ring bus and cross-bar, face high latency issues in memory access, which hinder performance as the number of cores increases.
Innovation Solution
A host interconnection device comprising a serializing module, analysis module, arbitration module, data-writing tracking module, and data-reading tracking module, which serializes and arbitrates read/write requests to reduce latency and increase bandwidth by directly connecting processing and chipset modules on-chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ring bus architecture is used for on-chip interconnection, then implementation is easy in physical process, but memory access latency becomes high
Solution Approach 1:
The patent segments the interconnection system into multiple core clusters, each with its own last-level cache, rather than having all cores share a single last-level cache. This segmentation allows each cluster to access its local cache independently, reducing contention and latency while maintaining ease of implementation through modular cluster design.
Solution Approach 2:
The patent introduces a new dimension to the interconnection architecture by adding a direct on-chip connection path between the chipset module and core clusters, parallel to the traditional ring bus path. This multi-path architecture allows data to traverse through the most efficient route, reducing latency without compromising the simplicity of the underlying physical implementation.
2Adaptability or versatility
If cross-bar architecture based on core cluster is used, then interconnection of larger number of cores is easier, but memory access latency remains high
Solution Approach 1:
The patent divides the system into multiple core clusters with dedicated last-level caches, reducing the scope of cache arbitration and memory access latency. Each cluster can independently manage its local resources, enabling scalable core interconnection without proportionally increasing access latency.
Solution Approach 2:
The patent implements a serialization module that pre-processes and orders memory access requests before they reach the arbitration stage. By serializing requests early in the pipeline, the system reduces arbitration complexity and latency, enabling efficient interconnection of larger numbers of cores while maintaining low access times.
3Productivity
If more cores are added to increase processing power, then computational capability improves, but cache access latency increases
Solution Approach 1:
The patent organizes cores into clusters, each with its own last-level cache, allowing cores within a cluster to access local cache resources with low latency. This segmentation enables the system to scale to more cores while maintaining acceptable access times through localized cache hierarchies.
Solution Approach 2:
The serialization module processes and prioritizes memory requests before arbitration, preparing the request queue in advance. This preliminary processing reduces the time required for arbitration and cache access, allowing the system to handle increased core counts without proportionally increasing latency.
Data Source
AI summary
A host interconnection device includes a serializing module, an analysis module, an arbitration module, a data-writing tracking module, and a data-reading tracking module. The serializing module serializes at least one first read/write request generated by at least one processing module and a second read/write request generated by a chipset module, and outputs the first read/write request or the second read/write request. The analysis module generates analysis information according to the first read/write request or the second read/write request. The arbitration module arbitrates the analysis information and snoop information, and generates arbitration information. The data-writing tracking module performs a data-writing tracking operation on the arbitration information to generate a first snoop request, a data-writing indication, and a data-writing request. The data-reading tracking module performs a data-reading tracking operation on the arbitration information to generate a second snoop request, a data-reading indication, and a data-reading request.