Host Interface Controller Ping-Pong Buffer Pre-Fetch

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Solution Overview

Problem

Conventional host interface controllers face inefficiencies during system startup and data access, particularly when handling repeated and sequential read requests from the central processing unit, leading to frequent command outputs and reduced performance.

Innovation Solution

The implementation of a host interface controller with a control module and two buffer sets operating in a ping-pong buffer mode, allowing for pre-fetching and buffering of data from a storage device, enabling efficient response to sequential read requests without frequent command outputs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional host interface controllers handle read requests sequentially without pre-fetching, then the system structure remains simple, but data access efficiency deteriorates due to frequent command outputs and system load increases

Engineering Contradiction:
Improvedata access efficiencyVSAvoidcontroller structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The host interface controller pre-fetches data from the storage device into buffer memory before the central processing unit actually requests it. This preliminary action allows data to be ready and waiting in the buffer, eliminating wait times and frequent command outputs, thereby improving data access efficiency without proportionally increasing system complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A buffer memory is introduced as an intermediary component between the storage device and the central processing unit. This buffer acts as a mediator that decouples the data transfer process, allowing the controller to manage data flow independently and reduce the frequency of commands sent to the storage device, thus improving efficiency while maintaining manageable device complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the host interface controller uses a single buffer for data storage, then the device complexity is low, but the productivity deteriorates due to inability to handle sequential read requests efficiently

Engineering Contradiction:
Improvesequential read request handlingVSAvoidbuffer set configuration
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The buffer memory is segmented into multiple buffer sets (first buffer set and second buffer set) that can operate independently. This segmentation allows the controller to manage different data streams or request sequences simultaneously, improving the ability to handle sequential read requests efficiently while keeping each individual buffer set relatively simple in structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The buffer sets operate in a ping-pong mode with periodic switching between them. While one buffer set is being filled with pre-fetched data, the other buffer set serves ongoing read requests, and vice versa. This periodic action ensures continuous data availability for sequential reads without requiring a single large complex buffer, thus improving productivity with manageable device complexity

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9910598B2Host interface controller and control method for storage device
Publication Date: 2018.03.06 VIA ALLIANCE SEMICON CO LTD
  • US9910598B2 patent drawing
  • US9910598B2 patent drawing
  • US9910598B2 patent drawing

AI summary

A host interface controller having a first buffer set and a second buffer set operated in a ping-pong buffer mode by a control module to alternately work as a pre-fetch buffer set. When one buffer set between the first buffer set and the second buffer set works as the pre-fetch buffer set, the control module pre-fetches and buffers data starting from a first address of a storage device into the pre-fetch buffer set and accesses the other buffer set between the first buffer set and the second buffer set to respond to a read request that the central processing unit issues to access data of a second address of the storage device.