Host Interface Device Power Supply Control for Storage Safety

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Solution Overview

Problem

The existing host interface technologies fail to prevent damage to storage devices due to abnormal power supply when devices of different standards are mounted on connectors, leading to potential damage from over-current issues.

Innovation Solution

A host interface device with a power supply control system that includes memory detection circuits and voltage supply circuits, which block voltage supply to uncompatible storage devices, ensuring safe power delivery by detecting the standard of the connected storage device through specific pin configurations and signal levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a connector is designed to support multiple standards, then versatility is improved, but reliability deteriorates due to abnormal power supply to incompatible devices

Engineering Contradiction:
Improveconnector compatibilityVSAvoidpower supply safety
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements memory detection circuits that perform preliminary detection of the storage device type before power supply is activated. The detection circuits check for the presence and state of detection pins, and only enable power supply when a compatible device is confirmed, preventing abnormal power supply to incompatible devices while maintaining multi-standard connector design

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces memory detection circuits as intermediary components between the connector and the power supply. These circuits act as mediators that detect device compatibility through detection pins and control the power supply switching elements accordingly, enabling the connector to support multiple standards while ensuring reliable power supply control

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If power supply is enabled immediately upon connection, then productivity is improved, but harmful factors increase due to potential over-current damage

Engineering Contradiction:
Improvepower supply speedVSAvoidover-current damage
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent implements preliminary detection through memory detection circuits that check device compatibility before enabling power supply. This preliminary action ensures that power is supplied quickly to compatible devices while preventing over-current damage to incompatible devices by verifying device presence and type before power activation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs feedback mechanisms where memory detection circuits continuously monitor the state of detection pins and provide feedback to control power supply switching elements. This feedback system enables rapid power supply to compatible devices while automatically preventing power supply to incompatible devices, balancing productivity and safety

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11163348B2Connectors that connect a storage device and power supply control device, and related power supply control devices and host interface devices
Publication Date: 2021.11.02 SAMSUNG ELECTRONICS CO LTD
  • US11163348B2 patent drawing
  • US11163348B2 patent drawing
  • US11163348B2 patent drawing

AI summary

Host interface devices are provided. A host interface device includes a first pin connected to a first node and a second pin connected to a second node. The host interface device includes a switch connected between the second node and a first voltage terminal, and configured to provide a voltage from the first voltage terminal to the second pin in response to a voltage level of the first node. The host interface device includes a pull-up resistor connected between the first node and a second voltage terminal. Moreover, the host interface device is configured to receive a memory detection signal from a storage device via the first pin when the first pin is electrically connected to the storage device.