Host Device IO Selection Using Buffer Availability

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Solution Overview

Problem

Storage systems face performance issues due to cache-related deficiencies, particularly when there is a shortage of available buffers of specific sizes, leading to delays and inefficiencies in processing IO operations.

Innovation Solution

Host devices are configured to select IO operations based on storage-side buffer availability information, temporarily prioritizing operations that match available buffer sizes to prevent delays and allow the storage system time to configure additional buffers, thereby alleviating cache-related issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the storage system uses local caches to process IO requests, then processing speed is improved, but cache-related issues such as buffer deficiencies adversely impact performance

Engineering Contradiction:
ImproveIO processing speedVSAvoidperformance stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The storage system sends buffer availability information back to host devices, enabling hosts to make informed IO submission decisions. This feedback loop allows the system to dynamically adjust IO patterns based on current cache buffer status, preventing performance degradation when buffers are deficient.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Host devices proactively query buffer availability information before submitting IO operations and use this information to pre-select appropriate IO operations. By performing this selection in advance based on known buffer status, the system avoids the performance penalties that would occur if buffer deficiencies were discovered only after IO submission.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If the storage system configures additional buffers of a particular size, then buffer availability is improved, but IO operations of other sizes are delayed

Engineering Contradiction:
Improvenumber of available buffersVSAvoidIO operation delay
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The host device dynamically adjusts its IO operation selection based on real-time buffer availability information. When the storage system is configuring additional buffers, the host temporarily modifies its IO submission pattern to match available buffer sizes, then returns to normal operation once buffers are replenished. This dynamic adaptation minimizes delays while ensuring buffer availability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The host device changes the size parameter of submitted IO operations to match the sizes of currently available buffers in the storage system. By adjusting this parameter based on buffer availability information, the host ensures that IO operations can be immediately processed without causing delays, while still allowing the storage system time to configure additional buffers of needed sizes.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If the host device prioritizes IO operations matching available buffer sizes, then buffer utilization efficiency is improved, but IO operations requiring other buffer sizes experience delays

Engineering Contradiction:
Improvebuffer utilization efficiencyVSAvoidIO operation delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The host device periodically queries the storage system for updated buffer availability information and adjusts its IO operation selection accordingly. This periodic reassessment allows the host to temporarily prioritize operations matching current buffer sizes, then switch back to normal operation patterns once buffers are replenished, minimizing overall delays while maintaining high buffer utilization efficiency during critical periods.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12001714B2Host device IO selection using buffer availability information obtained from storage system
Publication Date: 2024.06.04 DELL PROD LP
  • US12001714B2 patent drawing
  • US12001714B2 patent drawing
  • US12001714B2 patent drawing

AI summary

An apparatus in one embodiment comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to obtain buffer availability information from a storage system, the buffer availability information indicating that the storage system is currently experiencing a deficiency in a number of available buffers of a given one of at least first and second different buffer sizes supported by the storage system, and to select particular input-output operations for delivery to the storage system over one or more networks based at least in part on the obtained buffer availability information. Obtaining the buffer availability information from the storage system illustratively comprises sending at least one command from a host device to the storage system. First and second different buffer types having the first and second different buffer sizes may comprise respective different write buffer types within a larger write buffer.