Host-Side L2P Caching for Lower Flash Address-Mapping Latency

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Solution Overview

Problem

Latency associated with reading data from flash memory devices adversely impacts user experience in host devices due to inefficient management of logical-to-physical address mappings.

Innovation Solution

Implementing a hybrid caching system at the host device that includes a logical-to-physical (L2P) cache and a secondary cache, where regions of the L2P cache are evicted and their sub-regions are retained in the secondary cache based on access metrics, reducing memory access latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the L2P cache is used to store address mappings, then address mapping speed is improved, but cache memory is consumed and latency occurs when cache regions are removed

Engineering Contradiction:

Improveaddress mapping speedVSAvoidmemory access latency

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The L2P cache is divided into multiple regions, allowing selective eviction of specific regions while retaining others. This segmentation enables the system to maintain frequently accessed mappings in the cache while storing less frequently accessed mappings in secondary storage, thus reducing overall latency without completely depleting cache resources.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A hierarchical caching structure is implemented where the L2P cache contains multiple regions, and evicted regions are nested in secondary storage. This nested arrangement allows the system to maintain a multi-level cache hierarchy, where hot data resides in the L2P cache and cold data is nested in secondary storage, enabling fast access when needed while managing cache memory efficiently.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Quantity of substance

If regions are removed from the L2P cache to make space, then cache memory availability is improved, but access latency increases due to cache misses

Engineering Contradiction:

Improvecache memory availabilityVSAvoidaccess latency

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The system performs preliminary actions by pre-fetching or pre-positioning address mappings in the L2P cache before they are actually needed. This allows the cache to be proactively populated with mappings that are likely to be accessed soon, reducing the likelihood of cache misses and associated latency when actual access occurs.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

When regions are evicted from the L2P cache, their contents are copied to secondary storage rather than being completely discarded. This copying mechanism ensures that the data can be quickly reloaded into the cache if needed again, minimizing the performance impact of cache evictions while maintaining cache memory availability for other data.

Inventive Principle:

Principle #26Copying

Data Source

PatentUS12417023B2Host device caching of flash memory address mappings

Publication Date: 2025.09.16 QUALCOMM INC

AI summary

A host device includes system memory that includes a logical-to-physical (L2P) cache and a second cache. The host device also includes a host controller interface (HCI) configured to be coupled to a flash memory device. The HCI is configured to determine that a particular region of a L2P address mapping table is to be removed from the L2P cache. The L2P address mapping table is configured to include mappings between logical memory addresses and physical memory addresses of the flash memory device. The HCI is also configured to identify a particular sub-region of the particular region having an access metric that satisfies a retention criterion. The HCI is further configured to store the particular sub-region into the second cache. The HCI is also configured to remove the particular region from the L2P cache.