Host L2P Mapping Updates for Low-Latency Flash Data Erase
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Solution Overview
Problem
Current memory systems face increased power consumption and latency due to numerous messages during erase operations between host devices and memory devices, which is inefficient and undesirable.
Innovation Solution
The host device invalidates logical block addresses and shares invalidated region information using commands like Command UFS Protocol Information Unit (UPIU) or Host Performance Booster (HPB) write commands, updating the logical to physical (L2P) mapping table to reduce bus communications and synchronize with the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the host device and memory device exchange numerous messages during erase operations to maintain synchronization, then data erasure reliability is improved, but power consumption increases and I/O latency increases
Solution Approach 1:
The patent extracts the mapping table update operation from the sequential message exchange process and performs it independently at the host device before the erase operation. By pre-updating the L2P mapping table at the host and only syncing the relevant invalidated region information to the memory device, the system eliminates numerous synchronization messages while maintaining data erasure reliability through the preserved mapping relationship.
2Reliability
If the host device and memory device exchange numerous messages during erase operations to maintain synchronization, then data erasure reliability is improved, but I/O latency increases
Solution Approach 1:
The patent applies preliminary action by updating the L2P mapping table at the host device before initiating the erase operation. The host device pre-processes the mapping information and identifies invalidated regions in advance, then transmits only this condensed information to the memory device. This preliminary update eliminates the need for multiple back-and-forth synchronization messages during the erase operation, significantly reducing I/O latency while preserving data erasure reliability.
3Measurement precision
If the host device transmits detailed invalidated region information to the memory device, then mapping table synchronization accuracy is improved, but UFS bus bandwidth usage increases
Solution Approach 1:
The patent uses copying by creating a condensed representation of the invalidated region information at the host device and transmitting this copy to the memory device. Instead of transmitting the entire detailed mapping table or all invalidated region data, the system transmits a summarized copy containing only the essential synchronization information needed at the memory device, thereby maintaining synchronization accuracy while minimizing bus communication volume.
Data Source
AI summary
This disclosure provides systems, methods, and devices for memory systems that support erasing data in a memory device using an update on a mapping table in a host device. In a first aspect, a method of erasing data in a flash memory system includes a host memory controller receiving a request to erase data on a memory device; and transmitting an update on a mapping table in the host device to the memory device, the update on the mapping table being associated with the data. Other aspects and features are also claimed and described.