Host-Level Cache for Nonvolatile Memory Read Speed
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Solution Overview
Problem
Traditional storage systems with nonvolatile memory require long read times, which can be mitigated by hardware caches but at increased cost, necessitating a cost-effective alternative.
Innovation Solution
Implementing a host-level cache system using a smaller volatile memory device as a cache for a nonvolatile memory device, with a host device generating a cache table to read data by units of byte via a bus interface, eliminating the need for hardware caches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a hardware cache is used to reduce read time, then read speed is improved, but cost increases
Solution Approach 1:
The patent introduces a host-level cache as an intermediary between the host and nonvolatile memory. The host device includes a volatile memory device that acts as a cache, and a cache controller that manages data transfer between the nonvolatile memory and the volatile cache, enabling fast read access without requiring expensive hardware cache in the storage device
Solution Approach 2:
The patent replaces the traditional hardware cache mechanism (electrical/electronic caching at the storage device level) with a software-controlled host-level caching system. The cache controller uses command processing and data management software to achieve caching functionality, substituting mechanical/electrical hardware caching with a software-based approach
2Quantity of substance
If storage capacity of nonvolatile memory is increased, then storage capacity is improved, but hardware cache cost increases
Solution Approach 1:
The host device provides its own caching service through the volatile memory device and cache controller. Instead of relying on the storage device to provide hardware cache, the host independently manages its own cache, allowing the storage device to focus on providing大容量 nonvolatile memory without the burden of expensive hardware cache
Data Source
AI summary
A storage system includes a storage device and a host device. The storage device includes a nonvolatile memory device having a first size and a first volatile memory device having a second size smaller than the first size and configured to operate as a cache memory with respect to the nonvolatile memory device. The first volatile memory device is configured to allow a first bus portion access to cache data stored in the first volatile memory device. The host device is configured to generate a cache table corresponding to information in the cache data stored in the first volatile memory device and configured to read the cache data stored in the first volatile memory device via the first bus portion based on the cache table.