Host Machine Allocating Module Latency Rating Clustering

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Solution Overview

Problem

In disaggregated hardware systems, the non-uniform access latency between CPU and memory units leads to unpredictable performance of host machines, as resources are pooled and allocated dynamically, making it challenging to ensure consistent performance across different host machines.

Innovation Solution

A Host Machine Allocating Module manages latency ratings for pairs of CPU and memory units, distributing them into clusters based on latency ratings to ensure predictable performance by allocating CPU and memory units that match specific latency requirements, thereby achieving uniform performance across host machines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If resources are pooled and allocated dynamically in a disaggregated hardware system, then resource flexibility and adaptability are improved, but access latency between CPU and memory units becomes non-uniform and unpredictable

Engineering Contradiction:
Improveresource allocation flexibilityVSAvoidperformance predictability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system performs preliminary actions by measuring and recording latency ratings between CPU units and memory units before allocation occurs. These pre-measured latency values are stored in a latency rating table, enabling the allocation module to make informed decisions about which CPU-memory pairs to assign together, thereby ensuring predictable performance while maintaining dynamic allocation flexibility

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention applies local quality by recognizing that different CPU-memory pairs have different latency characteristics. Instead of treating all memory units uniformly, the system assigns memory units to specific CPU units based on their individual latency ratings, creating localized optimal pairs that ensure consistent performance for each host machine while allowing global resource flexibility

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If host machines are allocated with identical numbers of CPUs and memory units, then allocation simplicity is improved, but performance becomes non-uniform due to varying access latencies

Engineering Contradiction:
Improveallocation simplicityVSAvoidperformance uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The system changes the allocation parameters from simple counts of CPU and memory units to a more sophisticated distribution based on latency ratings. The allocation module uses latency rating thresholds to distribute CPU-unit and memory-unit pairs, ensuring that host machines receive combinations with similar average latency characteristics, thereby achieving uniform performance while maintaining allocation simplicity through automated decision-making

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11048557B2Methods and modules relating to allocation of host machines
Publication Date: 2021.06.29 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US11048557B2 patent drawing
  • US11048557B2 patent drawing
  • US11048557B2 patent drawing

AI summary

Methods, computer-readable media, and systems are included for generating information about latency ratings corresponding to a memory pool and a CPU pool. An example method includes for each CPU of the CPU pool, estimating a first latency rating for said each CPU towards the memory pool, and for each memory unit of the memory pool, estimating a second latency rating for said each memory unit towards the CPU pool. The CPUs are organized into a first plurality of groups of CPUs based on the estimated first latency rating, where each CPU of each group of the first plurality of groups has a first common latency rating towards the memory pool. The memory units are organized into a second plurality of groups of memory units based on the estimated second latency rating, where each memory unit of each group of the second plurality of groups has a second common latency rating towards the CPU pool.