Host-Managed Physical Address Mapping Without Storage FTL
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Solution Overview
Problem
Existing storage systems rely on a flash translation layer (FTL) in the storage device to manage mapping between logical and physical addresses, which can lead to inefficiencies and increased complexity.
Innovation Solution
A storage system where the host manages the physical data locations directly through a lookup table (LUT) that associates data identification information with physical addresses, eliminating the need for a flash translation layer in the storage device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a flash translation layer (FTL) is used in the storage device to manage mapping between logical and physical addresses, then the storage device can automatically handle address translation, but the system complexity increases and performance efficiency decreases
Solution Approach 1:
The patent extracts and removes the FTL component from the storage device, transferring the address translation function to the host side. This eliminates the complexity of having both FTL layers (device-side and host-side) while maintaining automatic address translation capability through the host's lookup table mechanism.
Solution Approach 2:
The patent merges the address translation function into the host's existing memory management structures by using a lookup table (LUT) that maps logical block addresses to physical block addresses. This consolidation eliminates the need for a separate FTL in the storage device, reducing overall system complexity.
2Extent of automation
If a flash translation layer (FTL) is used in the storage device, then address translation can be handled at the device level, but the host's management burden increases due to complex mapping operations
Solution Approach 1:
The patent extracts the address translation responsibility from the storage device and places it in the host. The host maintains a lookup table that maps logical block addresses to physical block addresses, thereby reducing the storage device's complexity while managing the mapping burden at the host level where it can leverage existing memory management capabilities.
3Adaptability or versatility
If a flash translation layer (FTL) is used to manage physical data locations, then the storage device can autonomously manage data placement, but the overall system efficiency decreases due to additional translation overhead
Solution Approach 1:
The patent extracts the FTL functionality from the storage device and implements it in the host using a lookup table. This eliminates the double translation overhead that occurs when both device and host have translation layers, thereby improving data access efficiency while maintaining the storage device's autonomy through simplified direct physical address access.
4Ease of operation
If a flash translation layer (FTL) is implemented in the storage device, then logical to physical address mapping can be performed at the device level, but the need for complex address translation processes increases
Solution Approach 1:
The patent removes the FTL from the storage device and implements address mapping in the host using a lookup table stored in memory. This eliminates the need for complex FTL operations within the device while maintaining automatic mapping functionality through the host's memory-based translation mechanism.
Data Source
AI summary
A storage system includes a host including a processor and a memory unit, and a storage device including a controller and a non-volatile memory unit. The processor is configured to output a write command, write data, and size information of the write data, to the storage device, the write command that is output not including a write address. The controller is configured to determine a physical write location of the non-volatile memory unit in which the write data are to be written, based on the write command and the size information, write the write data in the physical write location of the non-volatile memory unit, and output the physical write location to the host. The processor is further configured to generate, in the memory unit, mapping information between an identifier of the write data and the physical write location.