Host-Managed FTL for Defective Block and Read Latency Control
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Solution Overview
Problem
The increase in defective blocks in nonvolatile memory storage devices leads to increased replacement information and read latency, degrading the I/O performance of computing systems.
Innovation Solution
A computing system architecture where the host manages a global FTL for logical-to-physical address translation and garbage collection, while the storage device handles low-level abstraction and parallel operations, avoiding defective blocks and reducing address translation overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the storage device uses replacement processing to replace defective blocks with other blocks, then the reliability of the storage device is improved, but the read latency time increases and I/O performance degrades
Solution Approach 1:
The host performs preliminary actions by managing a global FTL that translates logical addresses to physical addresses in advance, and by executing garbage collection operations before they are needed. This pre-processing reduces the need for real-time address translation and block replacement during I/O operations, thereby reducing read latency while maintaining reliability.
Solution Approach 2:
The patent introduces an intermediary approach where the host and storage device share responsibilities through a hybrid FTL system. The host manages global address translation and garbage collection, while the storage device handles low-level abstraction and parallel operations. This intermediary coordination reduces the burden on the storage device during replacement processing, minimizing read latency impacts.
2Reliability
If the storage device increases replacement information to replace defective blocks, then the reliability is improved, but the I/O performance degrades due to increased address translation overhead
Solution Approach 1:
The patent segments the FTL functionality into two parts: a global FTL managed by the host for high-level address translation, and a local FTL managed by the storage device for low-level block mapping. This segmentation reduces the complexity of address translation by distributing the workload, allowing the host to handle global translation while the storage device manages local replacement information efficiently.
Solution Approach 2:
The host's global FTL serves multiple functions: it performs logical-to-physical address translation, manages garbage collection operations, and coordinates with the storage device's local FTL. This multi-functionality reduces the need for separate complex address translation mechanisms, thereby reducing overall device complexity while maintaining reliability through comprehensive address management.
Data Source
AI summary
According to one embodiment, a computing system transmits to a storage device a write request designating a first logical address for identifying first data to be written and a length of the first data. The computing system receives from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block by the storage device, and a first physical storage location in the first block to which the first data is written. The computing system updates a first table which manages mapping between logical addresses and physical addresses of the storage device and maps the first physical address to the first logical address.