Host Memory Buffer for Non-Volatile Memory Write Amplification
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Solution Overview
Problem
Flash memory devices face challenges with write amplification, where frequent writing and erasing of single-level cells (SLCs) lead to rapid increase in erase counts, potentially damaging the memory and reducing its lifetime, due to the need to move SLC data to multi-level cells (MLCs) for higher storage capacity.
Innovation Solution
A data storage device with a controller that temporarily stores write data in a host memory buffer (HMB) instead of SLC blocks, allowing direct programming to MLC blocks without passing through SLCs, thereby reducing data transfer from SLCs to MLCs and minimizing erase counts, and uses a mapping table to manage logical addresses for efficient data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If write data is stored in SLC blocks before being moved to MLC blocks, then data can be temporarily cached with fast write speed, but the erase count of SLC blocks increases rapidly causing memory damage and reduced lifetime
Solution Approach 1:
The patent introduces a Host Memory Buffer (HMB) located in the host system memory as an intermediary storage location. Write data is temporarily stored in the HMB instead of being written to SLC blocks in the flash memory device. This intermediary buffer allows the flash memory device to respond quickly to write commands while avoiding frequent write/erase cycles on the SLC blocks, thus resolving the contradiction between fast write speed and memory lifetime.
Solution Approach 2:
The patent moves the temporary storage function from the device-side SLC blocks to the host-side system memory (HMB), effectively changing the spatial dimension of where temporary data resides. This dimensional shift allows the flash memory device to maintain fast write response without subjecting its own SLC blocks to excessive wear, as the HMB is managed separately by the host system.
2Productivity
If SLC blocks are used for temporary data storage, then write operations can be performed quickly, but frequent writing and erasing leads to write amplification and increased erase counts
Solution Approach 1:
The HMB serves as an intermediary that absorbs write operations, preventing them from directly impacting the SLC blocks. By storing temporary data in the host's system memory, the flash memory device avoids the write amplification effect that would occur if data were repeatedly written to and erased from SLC blocks, thus reducing erase counts while maintaining write productivity.
Solution Approach 2:
Instead of physically writing data to SLC blocks and then erasing them, the system creates a logical copy mechanism where data is stored in the HMB and managed through mapping tables. This copying approach allows the system to maintain the appearance of fast write operations while avoiding the physical erase cycles that cause wear and write amplification.
3Quantity of substance
If data is stored directly in MLC blocks without using SLC blocks, then storage capacity is maximized, but write speed decreases due to slower programming characteristics of MLC
Solution Approach 1:
The patent performs preliminary data preparation and temporary storage in the HMB before final programming to MLC blocks. By pre-processing data in the fast host memory and organizing it through mapping tables, the system prepares data in advance for MLC programming, thereby mitigating the slower write speed of MLC while maintaining high storage capacity utilization.
Solution Approach 2:
The HMB acts as an intermediary that decouples the fast write operations from the slower MLC programming process. Data can be quickly staged in the HMB and then programmed to MLC blocks at the MLC's native slower speed, allowing the system to maintain high storage capacity while accepting the inherent speed limitation of MLC programming without compounding it through additional SLC intermediary steps.
Data Source
AI summary
High-efficiency control technology for non-volatile memory. A non-volatile memory has single level cells (SLCs) and multiple level cells (e.g., MLCs or TLCs) and is controlled by a controller. According to the controller at the device end, a host allocates a system memory to provide a host memory buffer (HMB). The controller at the device end uses the HMB to buffer write data issued by the host, and then flushes the write data from the HMB to multi-level cells of the non-volatile memory without passing single level cells of the non-volatile memory to reduce write amplification problems due to the frequent use of the single-level cells.