Host Memory Caching for Non-Volatile Read Latency

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current Unified Memory Architecture (UMA) systems face inefficiencies in memory access and data transfer between host and device, particularly in handling read and write operations, which can lead to performance bottlenecks and increased memory costs.

Innovation Solution

A memory system architecture that includes a host with a first and second memory area, an interface unit, and a controller unit, which determines whether data is in the first memory area before transferring it, using a non-volatile memory and cache structures to optimize data access by copying or reading data directly from the NAND memory as needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If data is always transferred from non-volatile memory to host memory for reading, then data access is simplified, but transfer time and system performance deteriorate

Engineering Contradiction:
Improvedata access simplicityVSAvoiddata transfer time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The system pre-loads frequently accessed data from non-volatile memory to host memory before it is actually needed. The determination unit identifies data that will likely be read soon and transfers it in advance, so when the read command arrives, the data is already available in host memory, eliminating transfer delays.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the data transfer strategy based on real-time conditions. The determination unit evaluates whether to transfer data from non-volatile memory to host memory on-demand or in advance, flexibly switching between modes to optimize performance for different access patterns and system states.

Inventive Principle:
Principle #15Dynamics

2Speed

If cache memory is added in the memory system, then read speed is improved, but device complexity and memory system size increase

Engineering Contradiction:
Improveread speedVSAvoidmemory system structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The invention extracts the caching function from the memory system side and relocates it to the host side. Instead of adding cache memory to the memory system, the system utilizes existing host memory resources and the determination unit to identify and pre-load frequently accessed data, achieving caching benefits without increasing memory system complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The host memory serves multiple functions: it acts as both the operating memory for the host system and as a cache for frequently accessed data from non-volatile memory. The determination unit enables the host memory to dynamically function as a cache without requiring dedicated cache hardware, achieving multi-functionality with existing resources.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Loss of time

If data is pre-loaded to host memory, then read access time is reduced, but memory usage and energy consumption increase

Engineering Contradiction:
Improveread access timeVSAvoidenergy consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

Instead of pre-loading all possible data or using excessive caching strategies, the system applies partial pre-loading only for data that the determination unit identifies as likely to be accessed soon. This selective approach reduces unnecessary data transfers and energy consumption while still providing speed benefits for anticipated accesses.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9396141B2Memory system and information processing device by which data is written and read in response to commands from a host
Publication Date: 2016.07.19 KIOXIA CORP
  • US9396141B2 patent drawing
  • US9396141B2 patent drawing
  • US9396141B2 patent drawing

AI summary

According to embodiments a memory system is connectable to a host which includes a host controller and a host memory including a first memory area and a second memory area. The memory system includes an interface unit, a non-volatile memory, and a controller unit. The interface unit receives a read command and a write command. The controller unit writes write-data to the non-volatile memory according to the write command. The controller unit determines whether read-data requested by the read command is in the first memory area. If the read-data is in the first memory area, the controller unit causes the host controller to copy the read-data from the first memory area to the second memory area. If the read-data is not in the first memory area, the controller unit reads the read-data from the non-volatile memory and causes the host controller to store the read-data in the second memory area.