Host Memory Controller Mixed Volatile Non-Volatile Command Execution

The patent segments the command execution process by introducing separate device select signals for volatile memory (e.g., CAS for SDRAM) and non-volatile memory (e.g., CS for NAND flash). This segmentation allows independent timing control for each memory type, resolving the timing parameter conflicts that would otherwise occur on a fully shared bus, while maintaining the physical bus sharing to avoid excessive complexity.

The patent implements dynamic device selection where the memory controller dynamically assigns device select signals based on the target memory type for each command. The controller can switch between volatile and non-volatile memory addressing modes dynamically, allowing optimal timing parameters to be applied to each memory type without requiring dedicated physical buses, thus balancing complexity and efficiency.

The patent makes the device select signal lines multi-functional by using the same physical bus infrastructure for both volatile and non-volatile memory access. The controller multiplexes the bus resources, using different signal combinations and timing sequences to address different memory types. This universality reduces the need for completely separate signal lines while still providing optimized timing control for each memory type.

The memory controller acts as an intermediary that translates high-level memory access requests into device-specific timing sequences and select signals. It mediates between the host processor's uniform memory access model and the different timing requirements of volatile and non-volatile memory, generating the appropriate device select signals and timing parameters without requiring the host to manage the complexity directly.

The patent implements feedback mechanisms where the memory controller monitors the execution status and timing responses from both volatile and non-volatile memory devices. Based on this feedback, the controller can adjust timing parameters dynamically, retune command sequences, and handle timing variations gracefully. This feedback loop maintains optimized speeds while compensating for timing variations to preserve reliability.

The patent incorporates timing margins and buffer periods in the command sequences sent to different memory types. By anticipating potential timing variations and coordination challenges, the controller designs command sequences with built-in cushioning that prevents timing conflicts and ensures reliable execution even when parameter variations occur, thus maintaining both speed and reliability.