Host Memory ECC Selection for Address Translation Caching
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Solution Overview
Problem
Current memory systems face challenges in efficiently managing large address translation tables, leading to increased costs and decreased access performance due to the need for large RAM capacities and potential cache misses, which affect the reliability and efficiency of data storage and retrieval.
Innovation Solution
A memory system with a controller that dynamically selects an encoding scheme based on error correcting capabilities, using a combination of first and second encoding/decoding circuits to store and retrieve data in a host's memory region, optimizing the use of both volatile and non-volatile memory by adjusting error correction capabilities according to error detection and cache hit rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If large RAM capacity is used to store address translation tables, then access performance is improved, but system cost increases
Solution Approach 1:
The patent divides the address translation table storage into multiple segments: a first storage unit (RAM) for frequently accessed recent data with high error correction capability, and a second storage unit for less frequently accessed data with lower error correction capability. This segmentation allows the system to achieve fast access performance for critical data while reducing the total RAM capacity required, thereby resolving the contradiction between access performance and system cost.
2Reliability
If high error correcting capability is used, then data reliability is improved, but storage efficiency decreases
Solution Approach 1:
The patent applies different error correction capabilities to different storage units based on their specific requirements. The first storage unit uses high error correction capability (first encoding scheme) to ensure data reliability for frequently accessed address translation data, while the second storage unit uses lower error correction capability (second encoding scheme) to maintain storage efficiency for less critical data. This local differentiation resolves the contradiction between data reliability and storage efficiency by optimizing each storage unit according to its functional requirements.
3Productivity
If dynamic encoding scheme selection is implemented, then storage efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic encoding scheme selection through an encoding scheme determination unit that monitors cache hit rates and automatically adjusts which encoding scheme (first or second) is applied to data being stored. This dynamic adaptation allows the system to optimize storage efficiency based on actual usage patterns while managing complexity through automated decision-making logic, resolving the contradiction between storage efficiency and device complexity.
Data Source
AI summary
A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.