Host Memory ECC Selection for Address Translation Tables
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Solution Overview
Problem
Existing memory systems face challenges in efficiently managing and storing large address translation tables, leading to increased costs and decreased access performance due to the need for large RAM capacities and potential cache misses, which affect the reliability and efficiency of data storage.
Innovation Solution
A memory system with a controller that dynamically selects an encoding scheme based on error correcting capabilities, using a combination of first and second encoding/decoding circuits to store data in a host's memory region, optimizing the use of both error correction and storage efficiency by adapting to error conditions and cache performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large RAM capacity is used to store address translation tables, then data storage reliability is improved, but system cost increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the error correction code strength based on the type of data being stored. Address translation table entries use stronger error correction (e.g., BCH code with higher redundancy) while other data uses weaker correction. This selective approach maintains reliability for critical data while reducing the overall RAM capacity needed and associated costs.
Solution Approach 2:
The patent segments the memory system into different error correction zones based on data type. The controller divides the address translation table storage into regions with varying error correction capabilities, allowing critical translation data to have enhanced protection while non-critical data uses minimal correction, optimizing both reliability and cost.
2Reliability
If large RAM capacity is used to store address translation tables, then data storage reliability is improved, but access performance decreases due to cache misses
Solution Approach 1:
The patent changes the error correction parameters dynamically based on data access patterns and data type. By using stronger error correction specifically for address translation tables, the system ensures reliable data without needing to increase overall RAM capacity, thereby avoiding cache miss penalties and maintaining access performance.
3Reliability
If strong error correction is applied to all data, then data storage reliability is improved, but storage efficiency decreases
Solution Approach 1:
The patent implements local quality by applying different error correction strengths to different data regions. Address translation table entries receive strong error correction with higher redundancy ratios, while other data types use weaker correction or none at all. This localized approach ensures reliability where needed without sacrificing storage efficiency across the entire system.
Solution Approach 2:
The controller dynamically changes error correction parameters based on the data being processed. When storing address translation tables, it activates strong error correction modes with higher redundancy. For other data, it switches to weaker correction modes, optimizing the balance between reliability and storage efficiency for each data type.
Data Source
AI summary
A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.